/*** ATD0CTL23 - ATD 0 Control Register 23; 0x000002C2 ***/
typedef union {
 word Word;
 /* Overlapped registers: */
 struct {
 /*** ATD0CTL2 - ATD 0 Control Register 2; 0x000002C2 ***/
 union {
 byte Byte;
 struct {
 byte ACMPIE :1; /* ATD Compare Interrupt Enable */
 byte ASCIE :1; /* ATD Sequence Complete Interrupt Enable */
 byte ETRIGE :1; /* External Trigger Mode enable */
 byte ETRIGP :1; /* External Trigger Polarity */
 byte ETRIGLE :1; /* External Trigger Level/Edge control */
 byte ICLKSTP :1; /* Internal Clock in Stop Mode Bit */
 byte AFFC :1; /* ATD Fast Conversion Complete Flag Clear */
 byte :1; 
 } Bits;
 } ATD0CTL2STR;
 #define ATD0CTL2 _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Byte
 #define ATD0CTL2_ACMPIE _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ACMPIE
 #define ATD0CTL2_ASCIE _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ASCIE
 #define ATD0CTL2_ETRIGE _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ETRIGE
 #define ATD0CTL2_ETRIGP _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ETRIGP
 #define ATD0CTL2_ETRIGLE _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ETRIGLE
 #define ATD0CTL2_ICLKSTP _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.ICLKSTP
 #define ATD0CTL2_AFFC _ATD0CTL23.Overlap_STR.ATD0CTL2STR.Bits.AFFC
 
 #define ATD0CTL2_ACMPIE_MASK 1U
 #define ATD0CTL2_ASCIE_MASK 2U
 #define ATD0CTL2_ETRIGE_MASK 4U
 #define ATD0CTL2_ETRIGP_MASK 8U
 #define ATD0CTL2_ETRIGLE_MASK 16U
 #define ATD0CTL2_ICLKSTP_MASK 32U
 #define ATD0CTL2_AFFC_MASK 64U
 /*** ATD0CTL3 - ATD 0 Control Register 3; 0x000002C3 ***/
 union {
 byte Byte;
 struct {
 byte FRZ0 :1; /* Background Debug Freeze Enable Bit 0 */
 byte FRZ1 :1; /* Background Debug Freeze Enable Bit 1 */
 byte FIFO :1; /* Result Register FIFO Mode */
 byte S1C :1; /* Conversion Sequence Length 1 */
 byte S2C :1; /* Conversion Sequence Length 2 */
 byte S4C :1; /* Conversion Sequence Length 4 */
 byte S8C :1; /* Conversion Sequence Length 8 */
 byte DJM :1; /* Result Register Data Justification */
 } Bits;
 struct {
 byte grpFRZ :2;
 byte :1;
 byte :1;
 byte :1;
 byte :1;
 byte :1;
 byte :1;