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\r\n\/******************************************************************************************************************* \r\n*\u6587\u4ef6\u8bf4\u660e: \r\n*        \u7b2c\u4e8c\u4e2aCUDA\u7a0b\u5e8f------GPU\u8bbe\u5907\u6027\u80fd\u53c2\u6570\u7684\u67e5\u8be2 \r\n*\u5f00\u53d1\u73af\u5883: \r\n*        win7+OpenCv2.4.8+cudaToolkit5.0+CUDA SDK3.0+NIVIDA NVS 3100M \r\n*\u53c2\u8003\u624b\u518c: \r\n*        CUDA_ToolKit_Reference_Manual.pdf \r\n*\u65f6\u95f4\u5730\u70b9: \r\n*        \u9655\u897f\u5e08\u8303\u5927\u5b66 2017.1.8 \r\n*\u4f5c    \u8005: \r\n*        \u4e5d\u6708 \r\n*\u6a21\u5757\u8bf4\u660e: \r\n*        1--\u7531\u4e8e\u6211\u4eec\u5e0c\u671b\u5728\u3010\u8bbe\u5907\u3011\u4e0a\u3010\u5206\u914d\u5185\u5b58\u3011\u548c\u3010\u6267\u884c\u4ee3\u7801\u3011,\u56e0\u6b64\u5982\u679c\u5728\u7a0b\u5e8f\u4e2d\u80fd\u591f\u77e5\u9053\u8bbe\u5907\u62e5\u6709\u591a\u5c11\u3010\u5185\u5b58\u3011\u4ee5\u53ca\u5177\u5907 \r\n*           \u54ea\u4e9b\u529f\u80fd,\u90a3\u4e48\u5c06\u975e\u5e38\u7684\u6709\u7528 \r\n*        2--\u800c\u4e14,\u5728\u4e00\u53f0\u8ba1\u7b97\u673a\u4e0a\u62e5\u6709\u591a\u4e2a\u652f\u6301CUDA\u7684\u8bbe\u5907\u4e5f\u662f\u975e\u5e38\u5e38\u89c1\u7684\u60c5\u5f62\u3002\u5728\u8fd9\u4e9b\u60c5\u51b5\u4e2d,\u6211\u4eec\u5e0c\u671b\u901a\u8fc7\u67d0\u79cd\u65b9\u5f0f\u6765\u786e\u5b9a\u4f7f\u7528 \r\n*           \u7684\u662f\u54ea\u4e00\u4e2aGPU\u8bbe\u5907 \r\n*        3--\u5728\u6df1\u5165\u7814\u7a76\u5982\u4f55\u7f16\u5199\u3010\u8bbe\u5907\u4ee3\u7801\u3011\u4e4b\u524d,\u6211\u4eec\u9700\u8981\u901a\u8fc7\u67d0\u79cd\u673a\u5236\u6765\u5224\u65ad\u8ba1\u7b97\u673a\u4e2d\u5f53\u524d\u6709\u54ea\u4e9b\u8bbe\u5907,\u4ee5\u53ca\u6bcf\u4e2a\u8bbe\u5907\u90fd\u652f\u6301\u54ea \r\n*           \u4e9b\u529f\u80fd\u3002 \r\n*        4--\u5e78\u8fd0\u7684\u662f,\u6211\u4eec\u53ef\u4ee5\u901a\u8fc7\u4e00\u4e2a\u975e\u5e38\u7b80\u5355\u7684\u63a5\u53e3\u6765\u83b7\u5f97\u8fd9\u6837\u7684\u4fe1\u606f \r\n*        5--\u9996\u5148,\u6211\u4eec\u5e0c\u671b\u77e5\u9053\u5728\u7cfb\u7edf<\/a>\u4e2d\u6709\u591a\u5c11\u4e2a\u8bbe\u5907\u662f\u652f\u6301CUDA\u7684,\u5e76\u4e14\u8fd9\u4e9b\u8bbe\u5907\u80fd\u591f\u8fd0\u884c\u57fa\u4e8eCUDA C\u7f16\u5199\u7684\u3010\u6838\u51fd\u6570\u3011 \r\n*        6--\u8981\u83b7\u5f97CUDA\u8bbe\u5907\u7684\u6570\u91cf,\u53ef\u4ee5\u8c03\u7528cudaGetDeviceCount() \r\n*        7--\u5728\u8c03\u7528cudaGetDeviceCount()\u540e,\u53ef\u4ee5\u5bf9\u6bcf\u4e2a\u8bbe\u5907\u8fdb\u884c\u8fed\u4ee3\u3001\u5e76\u67e5\u8be2\u5404\u4e2a\u3010\u8bbe\u5907\u3011\u7684\u3010\u76f8\u5173\u4fe1\u606f\u3011\u3002CUDA\u8fd0\u884c\u65f6\u5c06\u8fd4\u56de\u4e00 \r\n*           \u4e2acudaDeviceProp\u7c7b\u578b\u7684\u7ed3\u6784,\u5176\u4e2d\u5305\u542b\u4e86\u8bbe\u5907\u7684\u76f8\u5173\u5c5e\u6027\u3002 \r\n********************************************************************************************************************\/  \r\n#include \"cuda_runtime.h\"                             \/\/\u30101\u3011CUDA\u8fd0\u884c\u65f6\u5934\u6587\u4ef6,\u5305\u542b\u4e86\u8bb8\u591a\u7684runtime API  \r\n#include \"device_launch_parameters.h\"  \r\n#include                              \/\/\u30102\u3011\u9a71\u52a8\u7c7b\u578b\u7684\u5934\u6587\u4ef6,\u5305\u542bcudaDeviceProp\u3010\u8bbe\u5907\u5c5e\u6027\u3011  \r\n#include                          \/\/\u30103\u3011cuda\u8fd0\u884c\u65f6API\u7684\u5934\u6587\u4ef6  \r\n#include \"stdio.h\"  \r\n#include   \r\n  \r\n\/******************************************************************************************************************* \r\n*\u6a21\u5757\u8bf4\u660e\uff1a \r\n*        \u63a7\u5236\u53f0\u5e94\u7528\u7a0b\u5e8f\u7684\u5165\u53e3\u51fd\u6570----Main\u51fd\u6570 \r\n*\u51fd\u6570\u8bf4\u660e: \r\n*cudaGetDeviceCount\u51fd\u6570\u539f\u578b: \r\n*        extern __host__ __cudart_builtin__ cudaError_t CUDARTAPI cudaGetDeviceCount(int *count) \r\n*\u51fd\u6570\u4f5c\u7528: \r\n*        \u4ee5*count\u7684\u5f62\u5f0f\u8fd4\u56de\u53ef\u7528\u4e8e\u6267\u884c\u7684\u8ba1\u7b97\u80fd\u529b\u5927\u4e8e\u7b49\u4e8e1.0\u7684\u8bbe\u5907\u6570\u91cf,\u5982\u679c\u4e0d\u5b58\u5728\u6b64\u8bbe\u5907,\u90a3\u4e48\u8fd9\u4e2a\u51fd\u6570\u5c06\u4f1a\u8fd4\u56decudaError \r\n*        -NoDevice \r\n********************************************************************************************************************\/  \r\nint main()  \r\n{  \r\n    cudaDeviceProp  strProp;                            \/\/\u30101\u3011\u5b9a\u4e49\u4e00\u4e2a\u3010\u8bbe\u5907\u5c5e\u6027\u7ed3\u6784\u4f53\u3011\u7684\u3010\u7ed3\u6784\u4f53\u53d8\u91cf\u3011  \r\n    int            iCount;  \r\n    cudaGetDeviceCount(&iCount);                        \/\/\u30102\u3011\u83b7\u5f97GPU\u8bbe\u5907\u7684\u6570\u91cf  \r\n    std::printf(\"The number of GPU = %d\\n\",iCount);  \r\n    for(int i=0;i \n 
\r\nstruct __device_builtin__ cudaDeviceProp  \r\n{  \r\n    char   name[256];                  \/**< ASCII string identifying device *\/  \r\n    size_t totalGlobalMem;             \/**< Global memory available on device in bytes *\/  \r\n    size_t sharedMemPerBlock;          \/**< Shared memory available per block in bytes *\/  \r\n    int    regsPerBlock;               \/**< 32-bit registers available per block *\/  \r\n    int    warpSize;                   \/**< Warp size in threads *\/  \r\n    size_t memPitch;                   \/**< Maximum pitch in bytes allowed by memory copies *\/  \r\n    int    maxThreadsPerBlock;         \/**< Maximum number of threads per block *\/  \r\n    int    maxThreadsDim[3];           \/**< Maximum size of each dimension of a block *\/  \r\n    int    maxGridSize[3];             \/**< Maximum size of each dimension of a grid *\/  \r\n    int    clockRate;                  \/**< Clock frequency in kilohertz *\/  \r\n    size_t totalConstMem;              \/**< Constant memory available on device in bytes *\/  \r\n    int    major;                      \/**< Major compute capability *\/  \r\n    int    minor;                      \/**< Minor compute capability *\/  \r\n    size_t textureAlignment;           \/**< Alignment requirement for textures *\/  \r\n    size_t texturePitchAlignment;      \/**< Pitch alignment requirement for texture references bound to pitched memory *\/  \r\n    int    deviceOverlap;              \/**< Device can concurrently copy memory and execute a kernel. Deprecated. Use instead asyncEngineCount. *\/  \r\n    int    multiProcessorCount;        \/**< Number of multiprocessors on device *\/  \r\n    int    kernelExecTimeoutEnabled;   \/**< Specified whether there is a run time limit on kernels *\/  \r\n    int    integrated;                 \/**< Device is integrated as opposed to discrete *\/  \r\n    int    canMapHostMemory;           \/**< Device can map host memory with cudaHostAlloc\/cudaHostGetDevicePointer *\/  \r\n    int    computeMode;                \/**< Compute mode (See ::cudaComputeMode) *\/  \r\n    int    maxTexture1D;               \/**< Maximum 1D texture size *\/  \r\n    int    maxTexture1DMipmap;         \/**< Maximum 1D mipmapped texture size *\/  \r\n    int    maxTexture1DLinear;         \/**< Maximum size for 1D textures bound to linear memory *\/  \r\n    int    maxTexture2D[2];            \/**< Maximum 2D texture dimensions *\/  \r\n    int    maxTexture2DMipmap[2];      \/**< Maximum 2D mipmapped texture dimensions *\/  \r\n    int    maxTexture2DLinear[3];      \/**< Maximum dimensions (width, height, pitch) for 2D textures bound to pitched memory *\/  \r\n    int    maxTexture2DGather[2];      \/**< Maximum 2D texture dimensions if texture gather operations have to be performed *\/  \r\n    int    maxTexture3D[3];            \/**< Maximum 3D texture dimensions *\/  \r\n    int    maxTextureCubemap;          \/**< Maximum Cubemap texture dimensions *\/  \r\n    int    maxTexture1DLayered[2];     \/**< Maximum 1D layered texture dimensions *\/  \r\n    int    maxTexture2DLayered[3];     \/**< Maximum 2D layered texture dimensions *\/  \r\n    int    maxTextureCubemapLayered[2];\/**< Maximum Cubemap layered texture dimensions *\/  \r\n    int    maxSurface1D;               \/**< Maximum 1D surface size *\/  \r\n    int    maxSurface2D[2];            \/**< Maximum 2D surface dimensions *\/  \r\n    int    maxSurface3D[3];            \/**< Maximum 3D surface dimensions *\/  \r\n    int    maxSurface1DLayered[2];     \/**< Maximum 1D layered surface dimensions *\/  \r\n    int    maxSurface2DLayered[3];     \/**< Maximum 2D layered surface dimensions *\/  \r\n    int    maxSurfaceCubemap;          \/**< Maximum Cubemap surface dimensions *\/  \r\n    int    maxSurfaceCubemapLayered[2];\/**< Maximum Cubemap layered surface dimensions *\/  \r\n    size_t surfaceAlignment;           \/**< Alignment requirements for surfaces *\/  \r\n    int    concurrentKernels;          \/**< Device can possibly execute multiple kernels concurrently *\/  \r\n    int    ECCEnabled;                 \/**< Device has ECC support enabled *\/  \r\n    int    pciBusID;                   \/**< PCI bus ID of the device *\/  \r\n    int    pciDeviceID;                \/**< PCI device ID of the device *\/  \r\n    int    pciDomainID;                \/**< PCI domain ID of the device *\/  \r\n    int    tccDriver;                  \/**< 1 if device is a Tesla device using TCC driver, 0 otherwise *\/  \r\n    int    asyncEngineCount;           \/**< Number of asynchronous engines *\/  \r\n    int    unifiedAddressing;          \/**< Device shares a unified address space with the host *\/  \r\n    int    memoryClockRate;            \/**< Peak memory clock frequency in kilohertz *\/  \r\n    int    memoryBusWidth;             \/**< Global memory bus width in bits *\/  \r\n    int    l2CacheSize;                \/**< Size of L2 cache in bytes *\/  \r\n    int    maxThreadsPerMultiProcessor;\/**< Maximum resident threads per multiprocessor *\/  \r\n};<\/pre> \n 
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