{"rsdb":{"rid":"378618","subhead":"","postdate":"0","aid":"264736","fid":"92","uid":"1","topic":"1","content":"<div id=\"cnblogs_post_body\" class=\"blogpost-body cnblogs-markdown\"> \n <p><strong>\u672c\u6b21\u6848\u4f8b\u662f\u6309\u7740\u5c0f\u6885\u54e5\u7684\u601d\u8def\u6765\u5199\u7684\uff0c\u90e8\u5206\u622a\u56fe\u548c\u6587\u5b57\u6765\u81ea\u5176\u6559\u5b66\u89c6\u9891\u3002<\/strong><br \/> \u8fd9\u6b21\u8bbe\u8ba1\u7684\u662f\u4e00\u4e2a\u80fd\u628a\u6309\u952e\u4fe1\u53f7\u8f93\u5165\u8f6c\u6362\u4e3a\u4e00\u4e2a\u6309\u952e\u4fe1\u53f7\u4e0b\u964d\u6cbf\u548c\u4e0a\u5347\u6cbf\u68c0\u6d4b\u8f93\u51fa\u3002<\/p> \n <h2 id=\"1\u72b6\u6001\u673a\u7684\u8bbe\u5b9a\">1\u3001\u72b6\u6001\u673a\u7684\u8bbe\u5b9a<\/h2> \n <p><img src=\"https:\/\/img2023.cnblogs.com\/blog\/2968697\/202301\/2968697-20230114235922031-1704211164.png\" alt=\"image\" loading=\"lazy\" \/><br \/> &nbsp;<\/p> \n <ul> \n  <li>\u7a7a\u95f2\u6001\uff1a\u7b49\u5f85\u6309\u952e\u4fe1\u53f7\u7684\u4e0b\u964d\u6cbf\uff0c\u82e5\u51fa\u73b0\u5219\u8fdb\u5165\u4e0b\u4e00\u4e2a\u72b6\u6001\u3002<\/li> \n  <li>\u6309\u4e0b\u6ee4\u6ce2\u72b6\u6001\uff1a\u8fdb\u884c20ms\u7684\u8ba1\u65f6\uff0c\u82e5\u572820ms\u7684\u8ba1\u65f6\u5185\u51fa\u73b0\u7684\u4e0a\u5347\u6cbf\u5219\u8868\u793a\u6309\u952e\u8fd8\u5728\u6296\u52a8\uff0c\u56de\u5230\u7a7a\u95f2\u6001\uff1a\u5426\u5219\u8fdb\u5165\u4e0b\u4e00\u4e2a\u72b6\u6001,\u5e76\u751f\u6210\u6309\u952e\u6309\u4e0b\u4fe1\u53f7\u3002<\/li> \n  <li>\u7b49\u5f85\u91ca\u653e\u72b6\u6001\uff1a\u5982\u679c\u5728\u8be5\u72b6\u6001\u4e0b\u51fa\u73b0\u4e0a\u5347\u6cbf\u4fe1\u53f7\u8fdb\u5165\u91ca\u653e\u6ee4\u6ce2\u72b6\u6001\u3002<\/li> \n  <li>\u91ca\u653e\u6ee4\u6ce2\u72b6\u6001\uff1a\u8fdb\u884c20ms\u7684\u8ba1\u65f6\uff0c\u82e5\u572820ms\u7684\u8ba1\u65f6\u5185\u51fa\u73b0\u7684\u4e0b\u964d\u6cbf\u5219\u8868\u793a\u6309\u952e\u8fd8\u5728\u6296\u52a8\uff0c\u56de\u5230\u7b49\u5f85\u91ca\u653e\u72b6\u6001\uff1a\u5426\u5219\u8fdb\u5165\u7a7a\u95f2\u6001\uff0c\u5e76\u751f\u6210\u6309\u952e\u91ca\u653e\u4fe1\u53f7\u3002<br \/> &nbsp;<\/li> \n <\/ul> \n <h2 id=\"2\u6a21\u5757\u4ee3\u7801\">2\u3001\u6a21\u5757\u4ee3\u7801<\/h2> \n <pre><code class=\"language-verilog\">`timescale 1ns \/ 1ps\n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\/\/ Company: \n\/\/ Engineer:Lclone\n\/\/ \n\/\/ Create Date: 2023\/01\/14 20:44:54\n\/\/ Design Name: \n\/\/ Module Name: key_filter\n\/\/ Project Name: \n\/\/ Target Devices: \n\/\/ Tool Versions: \n\/\/ Description: \n\/\/ \n\/\/ Dependencies: \n\/\/ \n\/\/ Revision:\n\/\/ Revision 0.01 - File Created\n\/\/ Additional Comments:\n\/\/ \n\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\n\n\nmodule key_filter(\n    input           Clk,\n    input           Rst_n,\n    input           Key_in,\n    output  reg    Key_press,\n    output  reg    Key_release\n    );\n    \n    reg [2:0]   key_sync;\n    always @(posedge Clk or negedge Rst_n) begin\n        if(Rst_n == 0)\n            key_sync &lt;= 0;\n        else\n            key_sync &lt;= {key_sync[1:0],Key_in};\/\/\u5ef6\u8fdf3\u62cd\uff0c\u51cf\u5c11\u4e9a\u7a33\u6001\u51fa\u73b0\u7684\u6982\u7387\u7684\u540c\u65f6\uff0c\u8fd8\u53ef\u4ee5\u6355\u83b7\u4e0a\u5347\u6cbf\u548c\u4e0b\u964d\u6cbf\n    end\n    \n    reg key_nedge;\n    reg key_pedge;\n    always @(posedge Clk or negedge Rst_n) begin\n        if(Rst_n == 0)\n            begin\n                key_nedge &lt;= 0;\n                key_pedge &lt;= 0;\n            end\n        else if(key_sync[2:1] == 2'b10 )\/\/\u4e0b\u964d\u6cbf\u6355\u83b7\n            key_nedge &lt;= 1'b1;\n        else if(key_sync[2:1] == 2'b01 )\/\/\u4e0a\u964d\u6cbf\u6355\u83b7\n            key_pedge &lt;= 1'b1;\n        else\n            begin\n                key_nedge &lt;= 0;\n                key_pedge &lt;= 0;\n            end\n    end\n    \n    parameter  CNT_20MS = 1_000_000;\n    reg [19:0]  cnt_20ms;\n    reg [ 1:0]  state;\n    always @(posedge Clk or negedge Rst_n) begin\n        if(Rst_n == 0)\n            begin\n                state &lt;= 0;\n                cnt_20ms &lt;= 0;\n                Key_press &lt;= 0;\n                Key_release &lt;= 0;\n            end\n        else case(state)\n            0:\n                begin\n                    Key_release &lt;= 0;\n                    if(key_nedge == 1)\n                        state &lt;= 1;\n                    else\n                        state &lt;= 0;\n                end\n            1:\n                begin\n                    if(cnt_20ms &lt; CNT_20MS &amp; key_pedge == 1)\n                        begin\n                            state &lt;= 0;\n                            cnt_20ms &lt;= 0;\n                        end\n                    else if(cnt_20ms == CNT_20MS - 1)\n                        begin\n                            state &lt;= 2;\n                            cnt_20ms &lt;= 0;\n                            Key_press &lt;= 1;\n                        end\n                    else\n                        cnt_20ms &lt;= cnt_20ms + 1'b1;\n                end\n            2:\n                begin\n                    Key_press &lt;= 0;\n                    if(key_pedge == 1)\n                        state &lt;= 3;\n                    else\n                        state &lt;= 2;\n                end\n            3:\n                begin\n                    if(cnt_20ms &lt; CNT_20MS &amp; key_nedge == 1)\n                        begin\n                            state &lt;= 2;\n                            cnt_20ms &lt;= 0;\n                        end\n                    else if(cnt_20ms == CNT_20MS - 1)\n                        begin\n                            state &lt;= 0;\n                            cnt_20ms &lt;= 0;\n                            Key_release &lt;= 1;\n                        end\n                    else\n                        cnt_20ms &lt;= cnt_20ms + 1'b1;\n                end\n            default:;\n        endcase\n    end\nendmodule\n<\/code><\/pre> \n <h2 id=\"3\u4eff\u771f\">3\u3001\u4eff\u771f<\/h2> \n <h3 id=\"1random\u51fd\u6570\u7684\u4f7f\u7528\">(1)$random\u51fd\u6570\u7684\u4f7f\u7528<\/h3> \n <p>rand = {$random(seed)} % 10_000_000;<\/p> \n <ul> \n  <li>\u8868\u793a\u751f\u62100-9_999_999\u8303\u56f4\u5185\u7684\u968f\u673a\u6570\u5e76\u8d4b\u503c\u7ed9rand\uff1b<\/li> \n  <li>1\u4e2aseed\u6570\u5bf9\u5e94\u77401\u4e2a\u7ec4\u6709\u7279\u5b9a\u987a\u5e8f\u6392\u5217\u7684\u968f\u673a\u6570\uff0c\u53ef\u4ee5\u901a\u8fc7\u8bbe\u5b9aseed\u7684\u503c\u6765\u590d\u73b0\u4e00\u7ec4\u968f\u673a\u6570\uff1b<\/li> \n  <li>\u53ef\u4ee5\u53bb\u6389\u82b1\u62ec\u53f7\u540e\u4f7f\u751f\u6210\u7684\u8303\u56f4\u53d8\u6210(-9_999_999) - 9_999_999;<\/li> \n <\/ul> \n <h3 id=\"2\u4eff\u771f\u4ee3\u7801\">(2)\u4eff\u771f\u4ee3\u7801<\/h3> \n <pre><code class=\"language-verilog\">`timescale 1ns \/ 1ps\n\nmodule key_filter_tb();\n\nreg clk_50m;\ninitial clk_50m &lt;= 1;\nalways #10 clk_50m &lt;= ~clk_50m;\n\nreg rst_n;\ninitial begin\n    rst_n &lt;= 0;\n    #200\n    rst_n &lt;= 1;\nend\n\nreg         key_in;\nwire        key_press;\nwire        key_release;\nkey_filter  key_filter_inst(\n    .Clk                (clk_50m),\n    .Rst_n              (rst_n),\n    .Key_in             (key_in),\n    .Key_press          (key_press),\n    .Key_release        (key_release)    \n    );\n    \ninitial begin\n    key_in &lt;= 1;\n    #400\n    press_key(1);\n    #20\n    press_key(2);\n    #20\n    press_key(3);\nend\n\nreg [31:0]rand;\ntask press_key;\n    input [3:0]seed;\n    begin\n        key_in = 1;\n        #20_000_000;\n        repeat(5)begin\n            rand = {$random(seed)} % 10_000_000;\n            #rand key_in = ~key_in;\n        end\n        \n        key_in = 0;\n        #40_000_000;\n        \n        repeat(5)begin\n            rand = {$random(seed)} % 10_000_000;\n            #rand key_in = ~key_in;\n        end\n        key_in = 1;\n        #40_000_000;\n    end\nend","orderid":"0","title":"\u57fa\u4e8e\u72b6\u6001\u673a\u7684\u6309\u952e\u6d88\u6296\u6a21\u5757(\u4e00)","smalltitle":"","mid":"0","fname":"Verilog","special_id":"0","bak_id":"0","info":"0","hits":"371","pages":"2","comments":"0","posttime":"2023-07-23 13:25:59","list":"1690089959","username":"admin","author":"","copyfrom":"","copyfromurl":"","titlecolor":"","fonttype":"0","titleicon":"0","picurl":"https:\/\/www.cppentry.com\/upload_files\/","ispic":"0","yz":"1","yzer":"","yztime":"0","levels":"0","levelstime":"0","keywords":"<A HREF='https:\/\/www.cppentry.com\/do\/search.php?type=keyword&keyword=%D3%DA%D7%B4%CC%AC' target=_blank>\u4e8e\u72b6\u6001<\/A>","jumpurl":"","iframeurl":"","style":"","template":"a:3:{s:4:\"head\";s:0:\"\";s:4:\"foot\";s:0:\"\";s:8:\"bencandy\";s:0:\"\";}","target":"0","ip":"119.59.235.169","lastfid":"0","money":"0","buyuser":"","passwd":"","allowdown":"","allowview":"","editer":"","edittime":"0","begintime":"0","endtime":"0","description":"\u57fa\u4e8e\u72b6\u6001\u673a\u7684\u6309\u952e\u6d88\u6296\u6a21\u5757","lastview":"1716081996","digg_num":"0","digg_time":"0","forbidcomment":"0","ifvote":"0","heart":"","htmlname":"","city_id":"0"},"page":"1"}