\u7b80\u4ecb<\/h1> \n \n -
\u5f00\u53d1\u677f\uff1aEGO1<\/p> <\/li> \n
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\u5f00\u53d1\u73af\u5883\uff1aWindows10 + Xilinx Vivado 2020<\/p> <\/li> \n
-
\u6570\u5b57\u903b\u8f91\u5927\u4f5c\u4e1a\u9898\u76ee 7\uff1a \u4e52\u4e53\u7403\u6bd4\u8d5b\u6a21\u62df\u673a\u7684\u8bbe\u8ba1<\/p> <\/li> \n
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\u4e52\u4e53\u7403\u6bd4\u8d5b\u6a21\u62df\u673a\u7528\u53d1\u5149\u4e8c\u6781\u7ba1\uff08LED\uff09\u6a21\u62df\u4e52\u4e53\u7403\u8fd0\u52a8\u8f68\u8ff9\uff0c\u662f\u7531\u7532\u4e59\u53cc\u65b9\u53c2\u8d5b\uff0c\u52a0\u4e0a\u88c1\u5224\u7684\u4e09\u4eba\u6e38\u620f\uff08\u4e5f\u53ef\u4ee5\u4e0d\u7528\u88c1\u5224\uff09\u3002<\/p> <\/li> \n <\/ul> \n
\u7ba1\u811a\u7ea6\u675f\u4ee3\u7801\uff1a<\/p> \n \n \u70b9\u51fb\u67e5\u770b\u4ee3\u7801<\/summary> \n set_property IOSTANDARD LVCMOS33 [get_ports CLK]\nset_property IOSTANDARD LVCMOS33 [get_ports hitA]\nset_property IOSTANDARD LVCMOS33 [get_ports hitB]\nset_property PACKAGE_PIN P17 [get_ports CLK]\nset_property PACKAGE_PIN P5 [get_ports hitA]\nset_property PACKAGE_PIN R1 [get_ports hitB]\n\nset_property IOSTANDARD LVCMOS33 [get_ports {ballLocation[5]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {ballLocation[4]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {ballLocation[0]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {ballLocation[3]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {ballLocation[2]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {ballLocation[1]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {ballLocation[7]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {ballLocation[6]}]\nset_property PACKAGE_PIN F6 [get_ports {ballLocation[7]}]\nset_property PACKAGE_PIN G4 [get_ports {ballLocation[6]}]\nset_property PACKAGE_PIN G3 [get_ports {ballLocation[5]}]\nset_property PACKAGE_PIN J4 [get_ports {ballLocation[4]}]\nset_property PACKAGE_PIN H4 [get_ports {ballLocation[3]}]\nset_property PACKAGE_PIN J3 [get_ports {ballLocation[2]}]\nset_property PACKAGE_PIN J2 [get_ports {ballLocation[1]}]\nset_property PACKAGE_PIN K2 [get_ports {ballLocation[0]}]\n\nset_property IOSTANDARD LVCMOS33 [get_ports speedA]\nset_property PACKAGE_PIN P4 [get_ports speedA]\nset_property IOSTANDARD LVCMOS33 [get_ports speedB]\nset_property PACKAGE_PIN N4 [get_ports speedB]\n\nset_property IOSTANDARD LVCMOS33 [get_ports {statusOut[3]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {statusOut[2]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {statusOut[1]}]\nset_property PACKAGE_PIN K1 [get_ports {statusOut[3]}]\nset_property PACKAGE_PIN H6 [get_ports {statusOut[2]}]\nset_property PACKAGE_PIN M1 [get_ports {statusOut[1]}]\nset_property PACKAGE_PIN K3 [get_ports {statusOut[0]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {statusOut[0]}]\n\nset_property IOSTANDARD LVCMOS33 [get_ports {LED1[5]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LED0[0]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LED0[3]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LED1[2]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LED0[6]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LEDBit[1]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LEDBit[4]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LEDBit[7]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LED1[6]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LED0[1]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LED1[3]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LED0[4]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LED0[7]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LED1[0]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LEDBit[2]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LEDBit[0]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LEDBit[5]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LED1[4]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LED0[2]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LED0[5]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LED1[","orderid":"0","title":"FPGA\uff1a\u4e52\u4e53\u7403\u6bd4\u8d5b\u6a21\u62df\u673a\u7684\u8bbe\u8ba1(\u4e00)","smalltitle":"","mid":"0","fname":"Verilog","special_id":"0","bak_id":"0","info":"0","hits":"450","pages":"5","comments":"0","posttime":"2023-07-23 13:26:01","list":"1690089961","username":"admin","author":"","copyfrom":"","copyfromurl":"","titlecolor":"","fonttype":"0","titleicon":"0","picurl":"https:\/\/www.cppentry.com\/upload_files\/","ispic":"0","yz":"1","yzer":"","yztime":"0","levels":"0","levelstime":"0","keywords":"FPGA<\/A>","jumpurl":"","iframeurl":"","style":"","template":"a:3:{s:4:\"head\";s:0:\"\";s:4:\"foot\";s:0:\"\";s:8:\"bencandy\";s:0:\"\";}","target":"0","ip":"119.59.235.169","lastfid":"0","money":"0","buyuser":"","passwd":"","allowdown":"","allowview":"","editer":"","edittime":"0","begintime":"0","endtime":"0","description":"FPGA\uff1a\u4e52\u4e53\u7403\u6bd4\u8d5b\u6a21\u62df\u673a\u7684\u8bbe\u8ba1","lastview":"1715085903","digg_num":"0","digg_time":"0","forbidcomment":"0","ifvote":"0","heart":"","htmlname":"","city_id":"0"},"page":"1"}
\u5f00\u53d1\u677f\uff1aEGO1<\/p> <\/li> \n
\u5f00\u53d1\u73af\u5883\uff1aWindows10 + Xilinx Vivado 2020<\/p> <\/li> \n
\u6570\u5b57\u903b\u8f91\u5927\u4f5c\u4e1a\u9898\u76ee 7\uff1a \u4e52\u4e53\u7403\u6bd4\u8d5b\u6a21\u62df\u673a\u7684\u8bbe\u8ba1<\/p> <\/li> \n
\u4e52\u4e53\u7403\u6bd4\u8d5b\u6a21\u62df\u673a\u7528\u53d1\u5149\u4e8c\u6781\u7ba1\uff08LED\uff09\u6a21\u62df\u4e52\u4e53\u7403\u8fd0\u52a8\u8f68\u8ff9\uff0c\u662f\u7531\u7532\u4e59\u53cc\u65b9\u53c2\u8d5b\uff0c\u52a0\u4e0a\u88c1\u5224\u7684\u4e09\u4eba\u6e38\u620f\uff08\u4e5f\u53ef\u4ee5\u4e0d\u7528\u88c1\u5224\uff09\u3002<\/p> <\/li> \n <\/ul> \n
\u7ba1\u811a\u7ea6\u675f\u4ee3\u7801\uff1a<\/p> \n \u70b9\u51fb\u67e5\u770b\u4ee3\u7801<\/summary> \n
set_property IOSTANDARD LVCMOS33 [get_ports CLK]\nset_property IOSTANDARD LVCMOS33 [get_ports hitA]\nset_property IOSTANDARD LVCMOS33 [get_ports hitB]\nset_property PACKAGE_PIN P17 [get_ports CLK]\nset_property PACKAGE_PIN P5 [get_ports hitA]\nset_property PACKAGE_PIN R1 [get_ports hitB]\n\nset_property IOSTANDARD LVCMOS33 [get_ports {ballLocation[5]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {ballLocation[4]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {ballLocation[0]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {ballLocation[3]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {ballLocation[2]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {ballLocation[1]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {ballLocation[7]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {ballLocation[6]}]\nset_property PACKAGE_PIN F6 [get_ports {ballLocation[7]}]\nset_property PACKAGE_PIN G4 [get_ports {ballLocation[6]}]\nset_property PACKAGE_PIN G3 [get_ports {ballLocation[5]}]\nset_property PACKAGE_PIN J4 [get_ports {ballLocation[4]}]\nset_property PACKAGE_PIN H4 [get_ports {ballLocation[3]}]\nset_property PACKAGE_PIN J3 [get_ports {ballLocation[2]}]\nset_property PACKAGE_PIN J2 [get_ports {ballLocation[1]}]\nset_property PACKAGE_PIN K2 [get_ports {ballLocation[0]}]\n\nset_property IOSTANDARD LVCMOS33 [get_ports speedA]\nset_property PACKAGE_PIN P4 [get_ports speedA]\nset_property IOSTANDARD LVCMOS33 [get_ports speedB]\nset_property PACKAGE_PIN N4 [get_ports speedB]\n\nset_property IOSTANDARD LVCMOS33 [get_ports {statusOut[3]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {statusOut[2]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {statusOut[1]}]\nset_property PACKAGE_PIN K1 [get_ports {statusOut[3]}]\nset_property PACKAGE_PIN H6 [get_ports {statusOut[2]}]\nset_property PACKAGE_PIN M1 [get_ports {statusOut[1]}]\nset_property PACKAGE_PIN K3 [get_ports {statusOut[0]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {statusOut[0]}]\n\nset_property IOSTANDARD LVCMOS33 [get_ports {LED1[5]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LED0[0]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LED0[3]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LED1[2]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LED0[6]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LEDBit[1]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LEDBit[4]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LEDBit[7]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LED1[6]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LED0[1]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LED1[3]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LED0[4]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LED0[7]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LED1[0]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LEDBit[2]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LEDBit[0]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LEDBit[5]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LED1[4]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LED0[2]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LED0[5]}]\nset_property IOSTANDARD LVCMOS33 [get_ports {LED1[","orderid":"0","title":"FPGA\uff1a\u4e52\u4e53\u7403\u6bd4\u8d5b\u6a21\u62df\u673a\u7684\u8bbe\u8ba1(\u4e00)","smalltitle":"","mid":"0","fname":"Verilog","special_id":"0","bak_id":"0","info":"0","hits":"450","pages":"5","comments":"0","posttime":"2023-07-23 13:26:01","list":"1690089961","username":"admin","author":"","copyfrom":"","copyfromurl":"","titlecolor":"","fonttype":"0","titleicon":"0","picurl":"https:\/\/www.cppentry.com\/upload_files\/","ispic":"0","yz":"1","yzer":"","yztime":"0","levels":"0","levelstime":"0","keywords":"FPGA<\/A>","jumpurl":"","iframeurl":"","style":"","template":"a:3:{s:4:\"head\";s:0:\"\";s:4:\"foot\";s:0:\"\";s:8:\"bencandy\";s:0:\"\";}","target":"0","ip":"119.59.235.169","lastfid":"0","money":"0","buyuser":"","passwd":"","allowdown":"","allowview":"","editer":"","edittime":"0","begintime":"0","endtime":"0","description":"FPGA\uff1a\u4e52\u4e53\u7403\u6bd4\u8d5b\u6a21\u62df\u673a\u7684\u8bbe\u8ba1","lastview":"1715085903","digg_num":"0","digg_time":"0","forbidcomment":"0","ifvote":"0","heart":"","htmlname":"","city_id":"0"},"page":"1"}