{"rsdb":{"rid":"396531","subhead":"","postdate":"0","aid":"273157","fid":"92","uid":"1","topic":"1","content":"<div id=\"cnblogs_post_body\" class=\"blogpost-body cnblogs-markdown\"> \n <h1 id=\"\u5b9e\u9a8c\u76ee\u7684\">\u5b9e\u9a8c\u76ee\u7684<\/h1> \n <ul> \n  <li>\u719f\u6089\u5e76\u638c\u63e1 MIPS \u8ba1\u7b97\u673a\u4e2d\u5bc4\u5b58\u5668\u5806\u7684\u539f\u7406\u548c\u8bbe\u8ba1\u65b9\u6cd5<\/li> \n  <li>\u7406\u89e3\u6e90\u64cd\u4f5c\u6570\/\u76ee\u7684\u64cd\u4f5c\u6570\u7684\u6982\u5ff5<\/li> \n <\/ul> \n <h1 id=\"\u5b9e\u9a8c\u73af\u5883\">\u5b9e\u9a8c\u73af\u5883<\/h1> \n <ul> \n  <li>Vivado \u96c6\u6210\u5f00\u53d1\u73af\u5883<\/li> \n <\/ul> \n <h1 id=\"mips\u5bc4\u5b58\u5668\">MIPS\u5bc4\u5b58\u5668<\/h1> \n <p><img src=\"https:\/\/pic.imgdb.cn\/item\/64f40fab661c6c8e5400bf9a.jpg\" alt=\"\" loading=\"lazy\" \/><\/p> \n <ul> \n  <li>\u5bc4\u5b58\u5668<strong>R0<\/strong>\u7684\u503c\u6052\u4e3a<strong>0<\/strong>\u3002<\/li> \n <\/ul> \n <h1 id=\"\u6a21\u5757\u63a5\u53e3\u8bbe\u8ba1\">\u6a21\u5757\u63a5\u53e3\u8bbe\u8ba1<\/h1> \n <p><strong>1\u4e2a\u5199\u7aef\u53e3\u548c2\u4e2a\u8bfb\u7aef\u53e3<\/strong><\/p> \n <p><img src=\"https:\/\/pic.imgdb.cn\/item\/64f41051661c6c8e5400ced2.jpg\" alt=\"\" loading=\"lazy\" \/><\/p> \n <table> \n  <thead> \n   <tr> \n    <th>\u540d\u79f0<\/th> \n    <th>\u5bbd\u5ea6<\/th> \n    <th>\u65b9\u5411<\/th> \n    <th>\u63cf\u8ff0<\/th> \n   <\/tr> \n  <\/thead> \n  <tbody> \n   <tr> \n    <td>clk<\/td> \n    <td>1<\/td> \n    <td>IN<\/td> \n    <td>\u65f6\u949f\u4fe1\u53f7<\/td> \n   <\/tr> \n   <tr> \n    <td>raddr1<\/td> \n    <td>5<\/td> \n    <td>IN<\/td> \n    <td>\u5bc4\u5b58\u5668\u5806\u8bfb\u5730\u57401<\/td> \n   <\/tr> \n   <tr> \n    <td>rdata1<\/td> \n    <td>32<\/td> \n    <td>OUT<\/td> \n    <td>\u5bc4\u5b58\u5668\u5806\u8fd4\u56de\u6570\u636e1<\/td> \n   <\/tr> \n   <tr> \n    <td>raddr2<\/td> \n    <td>5<\/td> \n    <td>IN<\/td> \n    <td>\u5bc4\u5b58\u5668\u5806\u8bfb\u5730\u57402<\/td> \n   <\/tr> \n   <tr> \n    <td>rdata2<\/td> \n    <td>32<\/td> \n    <td>OUT<\/td> \n    <td>\u5bc4\u5b58\u5668\u5806\u8fd4\u56de\u6570\u636e2<\/td> \n   <\/tr> \n   <tr> \n    <td>we<\/td> \n    <td>1<\/td> \n    <td>IN<\/td> \n    <td>\u5bc4\u5b58\u5668\u5806\u5199\u4f7f\u80fd<\/td> \n   <\/tr> \n   <tr> \n    <td>waddr<\/td> \n    <td>5<\/td> \n    <td>IN<\/td> \n    <td>\u5bc4\u5b58\u5668\u5806\u5199\u5730\u5740<\/td> \n   <\/tr> \n   <tr> \n    <td>wdata<\/td> \n    <td>32<\/td> \n    <td>IN<\/td> \n    <td>\u5bc4\u5b58\u5668\u5806\u5199\u6570\u636e<\/td> \n   <\/tr> \n  <\/tbody> \n <\/table> \n <p>\u5bc4\u5b58\u5668\u5806\uff08<strong>regfile<\/strong>\uff09\u5b9e\u73b0\u4e8632\u4e2a32\u4f4d\u901a\u7528\u5bc4\u5b58\u5668\u3002<\/p> \n <ul> \n  <li>\u53ef\u4ee5\u540c\u65f6\u8fdb\u884c\u4e24\u4e2a\u5bc4\u5b58\u5668\u7684\u8bfb\u64cd\u4f5c\u548c\u4e00\u4e2a\u5bc4\u5b58\u5668\u7684\u5199\u64cd\u4f5c\u3002<\/li> \n  <li>\u5199\uff1a\u5199\u4f7f\u80fd\u4fe1\u53f7\uff08we\uff09\u4e3a1\u65f6\u5199\u6709\u6548\uff0c\u4e3a0\u65f6\u65e0\u6548\u3002\uff08<strong>write enable<\/strong>\uff09<\/li> \n  <li>\u8bfb\uff1a\u8bfb\u64cd\u4f5c\u53ef\u4ee5\u540c\u65f6\u8bfb\u4e24\u4e2a\u5bc4\u5b58\u5668\u3002<\/li> \n  <li>\u540c\u65f6\u5bf9\u540c\u4e00\u4e2a\u5bc4\u5b58\u5668\u8fdb\u884c\u8bfb\u5199\u65f6\uff0c\u8bfb\u7684\u6570\u636e\u4e3a\u65e7\u7684\u6570\u636e\u3002<\/li> \n  <li>\u8bfb\u5199\u5747\u4e3a\u540c\u6b65\u3002<\/li> \n  <li>0\u53f7\u5bc4\u5b58\u5668\u6052\u4e3a0\u3002<\/li> \n <\/ul> \n <h1 id=\"\u8bbe\u8ba1\u4ee3\u7801\">\u8bbe\u8ba1\u4ee3\u7801<\/h1> \n <pre><code class=\"language-verilog\">`define REG_DATA_WIDTH 31:0\n`define REG_NUM 31:0\n`define REG_ADDR_WIDTH 4:0\n`define REG_ADDR_BIT 5 \/\/ \u5730\u5740\u7ebf\u5bbd\n`define REG_DATA_BIT 32 \/\/ \u6570\u636e\u7ebf\u5bbd\nmodule regfile(\n    input clk,\n    input [`REG_ADDR_WIDTH] raddr1,\n    input [`REG_ADDR_WIDTH] raddr2,\n    input we, \/\/ \u5199\u4f7f\u80fd\n    input [`REG_ADDR_WIDTH] waddr, \/\/ \u5199\u5730\u5740\n    input [`REG_DATA_WIDTH] wdata, \/\/ \u5199\u6570\u636e\n    output reg [`REG_DATA_WIDTH] rdata1,\n    output reg [`REG_DATA_WIDTH] rdata2\n    );\n    \n    \/\/ \u6570\u7ec4\u8868\u793a\u5bc4\u5b58\u5668\u5806\n    reg [`REG_DATA_WIDTH] mips_regfile [`REG_NUM];\n    \n    \/\/ \u8bfb1\n    always @(posedge clk) begin\n        if (raddr1 == {`REG_ADDR_BIT{1'b0}}) begin\n            rdata1 &lt;= {`REG_DATA_BIT{1'b0}};\n        end\n        else begin\n            rdata1 &lt;= mips_regfile[raddr1];\n        end\n    end\n    \/\/ \u8bfb2\n    always @(posedge clk) begin\n        if (raddr2 == {`REG_ADDR_BIT{1'b0}}) begin\n            rdata2 &lt;= {`REG_DATA_BIT{1'b0}};\n        end\n        else begin\n            rdata2 &lt;= mips_regfile[raddr2];\n        end\n    end\n    \/\/ \u5199\n    always @(posedge clk) begin\n        if (we == 1'b1 ) begin\n            if (waddr == {`REG_ADDR_BIT{1'b0}}) begin\n                mips_regfile[0] &lt;= {`REG_DATA_BIT{1'b0}};\n            end\n            else begin\n                mips_regfile[waddr] &lt;= wdata;       \n            end\n        end\n        else begin\n            mips_regfile[0] &lt;= {`REG_DATA_BIT{1'b0}};\n        end\n    end\n    \nendmodule\n\n<\/code><\/pre> \n <h1 id=\"\u6d4b\u8bd5\">\u6d4b\u8bd5<\/h1> \n <h3 id=\"\u6d4b\u8bd5\u4ee3\u7801\">\u6d4b\u8bd5\u4ee3\u7801<\/h3> \n <pre><code class=\"language-verilog\">`timescale 1ns \/ 1ps\n\n`define REG_DATA_WIDTH 31:0\n`define REG_NUM 31:0\n`define REG_ADDR_WIDTH 4:0\n`define REG_ADDR_BIT 5\n`define REG_DATA_BIT 32\nmodule sim();\n    reg clk;\n    reg [`REG_ADDR_WIDTH] raddr1;\n    reg [`REG_ADDR_WIDTH] raddr2;\n    reg we; \/\/ \u5199\u4f7f\u80fd\n    reg [`REG_ADDR_WIDTH] waddr; \/\/ \u5199\u5730\u5740\n    reg [`REG_DATA_WIDTH] wdata; \/\/ \u5199\u6570\u636e\n    wire [`REG_DATA_WIDTH] rdata1;\n    wire [`REG_DATA_WIDTH] rdata2;\n    \n    integer i;\n    regfile u0 (\n        .clk(clk),\n        .raddr1(raddr1),\n        .raddr2(raddr2),\n        .we(we),\n        .waddr(waddr),\n        .wdata(wdata),\n        .rdata1(rdata1),\n        .rdata2(rdata2)\n    );\n    initial begin\n        clk = 1;\n        forever begin\n            #10 clk = ~clk;\n        end\n    end\n    \n    initial begin\n        raddr1 = `REG_ADDR_BIT'd0;\n        raddr2 = `REG_ADDR_BIT'd0;\n        we = 1'b0;\n        waddr = `REG_ADDR_BIT'd0;\n        wdata = `REG_DATA_BIT'd0;\n        \n        \/\/ \u5199\u6570\u636e\n        #100 \n        we = 1'b1;\n        wdata = `REG_DATA_BIT'hFF;\n        for (i = 0; i &lt; `REG_DATA_BIT; i = i + 1) begin\n            waddr = i;\n            wdata = wdata + `REG_DATA_BIT'h100;\n            #20;\n        end\n        \/\/ \u8bfb\u6570\u636e\n        we = 1'b0;\n        \n        for (i = 0; i &lt; `REG_DATA_BIT; i = i + 1) begin\n            raddr1 = i;\n            raddr2 = `REG_DATA_BIT - raddr1 - 1;\n            #20;\n        end\n        \n        \/\/ \u8bfb\u5199\u76f8\u540c\n        \/\/ \u8bfb\u5230\u7684\u6570\u636e\u662f\u65e7\u6570\u636e\n        we = 1'b1;\n        wdata = `REG_DATA_BIT'h100;\n        for (i = 0; i &lt; `REG_DATA_BIT; i = i + 1) begin\n            raddr1 = i;\n            raddr2 = i;\n            waddr = i;\n            wdata = wdata - `REG_DATA_BIT'h1;\n            #20;\n        end\n        \n        we = 1'b0;\n        #100 $finish;\n        \n    end\nendmodule\n\n<\/code><\/pre> \n <h3 id=\"\u6d4b\u8bd5\u6ce2\u5f62\">\u6d4b\u8bd5\u6ce2\u5f62<\/h3> \n <p>\u5199\u6570\u636e\uff1a<\/p> \n <p>\u4ece 0\u53f7\u5bc4\u5b58\u5668\u5f00\u59cb\u5230 31\u53f7\u5bc4\u5b58\u5668\uff0c\u5206\u522b\u5199\u5165 <strong>01ff<\/strong>\u5230 20ff\u3002<\/p> \n <p><img src=\"https:\/\/pic.imgdb.cn\/item\/64f410c0661c6c8e5400dcd1.jpg\" alt=\"\" loading=\"lazy\" \/><\/p> \n <p>\u8bfb\u6570\u636e\uff1a<\/p> \n <p>\u8bfb\u5730\u5740 1\u548c\u8bfb\u5730\u5740 2\u5206\u522b\u8bfb\u5bc4\u5b58\u5668\u503c\uff0c0\u53f7\u5bc4\u5b58\u5668\u8bfb\u5f97\u503c\u4e3a 0\u3002\u5176\u4f59\u5bc4\u5b58\u5668\u8bfb\u503c\u6b63\u786e\u3002<\/p> \n <p><img src=\"https:\/\/pic.imgdb.cn\/item\/64f410da661c6c8e5400df6b.jpg\" alt=\"\" loading=\"lazy\" \/><\/p> \n <h3 id=\"\u7ed3\u679c\u5206\u6790\">\u7ed3\u679c\u5206\u6790<\/h3> \n <p>\u5148\u8fdb\u884c\u5199\u6570\u636e\u6d4b\u8bd5\uff0c\u4ece 0\u53f7\u5bc4\u5b58\u5668\u5f00\u59cb\u5230 31\u53f7\u5bc4\u5b58\u5668\uff0c\u5206\u522b\u5199\u5165 <strong>01ff<\/strong>\u5230 <strong>20ff<\/strong>\u3002\u7136\u540e\u8fdb\u884c\u8bfb\u6570\u636e\u6d4b\u8bd5\uff0c\u53d1\u73b0 0\u53f7\u5bc4\u5b58\u5668\u503c\u4e3a 0\uff0c\u5176\u4f59\u5bc4\u5b58\u5668\u7684\u503c\u7b26\u5408\u9884\u671f\u3002\u5f53\u540c\u65f6\u5199\u548c\u8bfb\uff0c\u5373\u5199\u5730\u5740\u548c\u8bfb\u5730\u5740\u76f8\u540c\uff0c\u4e14\u5199\u4f7f\u80fd\u65f6\uff0c\u53d1\u73b0\u8bfb\u5230\u7684\u6570\u636e\u4e3a\u65e7\u6570\u636e\uff0c\u800c\u5199\u5165\u7684\u6570\u636e\u4e0d\u4f1a\u51b2\u7a81\u3002<\/p> \n<\/div>","orderid":"0","title":"MIPS\u5bc4\u5b58\u5668\u5806","smalltitle":"","mid":"0","fname":"Verilog","special_id":"0","bak_id":"0","info":"0","hits":"281","pages":"1","comments":"0","posttime":"2023-09-09 10:25:26","list":"1694226326","username":"admin","author":"","copyfrom":"","copyfromurl":"","titlecolor":"","fonttype":"0","titleicon":"0","picurl":"https:\/\/www.cppentry.com\/upload_files\/","ispic":"0","yz":"1","yzer":"","yztime":"0","levels":"0","levelstime":"0","keywords":"<A HREF='https:\/\/www.cppentry.com\/do\/search.php?type=keyword&keyword=MIPS' target=_blank>MIPS<\/A>","jumpurl":"","iframeurl":"","style":"","template":"a:3:{s:4:\"head\";s:0:\"\";s:4:\"foot\";s:0:\"\";s:8:\"bencandy\";s:0:\"\";}","target":"0","ip":"101.232.55.135","lastfid":"0","money":"0","buyuser":"","passwd":"","allowdown":"","allowview":"","editer":"","edittime":"0","begintime":"0","endtime":"0","description":"MIPS\u5bc4\u5b58\u5668\u5806","lastview":"1716081959","digg_num":"0","digg_time":"0","forbidcomment":"0","ifvote":"0","heart":"","htmlname":"","city_id":"0"},"page":"1"}