typedef struct
{
UINT16 nMID; /* Manufacturer ID */
UINT16 nDID; /* Device ID */
UINT16 nNumOfBlks; /* Number of Blocks */
UINT16 nPgsPerBlk; /* Number of Pages per block */
UINT16 nSctsPerPg; /* Number of Sectors per page */
UINT16 nNumOfPlanes; /* Number of Planes */
UINT16 nBlksInRsv; /* The Number of Blocks in Reservior for Bad Blocks */
UINT8 nBadPos; /* BadBlock Information Poisition*/
UINT8 nLsnPos; /* LSN Position */
UINT8 nECCPos; /* ECC Policy : HW_ECC, SW_ECC */
UINT16 nBWidth; /* Nand Organization X8 or X16 */
UINT16 nTrTime; /* Typical Read Op Time */
UINT16 nTwTime; /* Typical Write Op Time */
UINT16 nTeTime; /* Typical Erase Op Time */
UINT16 nTfTime; /* Typical Transfer Op Time */
} FlashDevSpec;
static FlashDevSpec astNandSpec[] = {
/*************************************************************************/
/* nMID, nDID, */
/* nNumOfBlks */
/* nPgsPerBlk */
/* nSctsPerPg */
/* nNumOfPlanes */
/* nBlksInRsv */
/* nBadPos */
/* nLsnPos */
/* nECCPos */
/* nBWidth */
/* nTrTime */
/* nTwTime */
/* nTeTime */
/* nTfTime*/
/*************************************************************************/
/* 8Gbit DDP NAND Flash */
//{ 0xEC, 0xD3, 8192, 64, 4, 2,160, 0, 2, 8, BW_X08, 50, 350, 2000, 50},
{ 0xEC, 0xD3, 4096, 128, 4, 2,160, 0, 2, 8, BW_X08, 50, 350, 2000, 50},
/* 16Gbit DDP NAND Flash */
{ 0xEC, 0xD5, 4096, 128, 8, 2,160, 0, 2, 8, BW_X08, 50, 350, 2000, 50}, // 8192 gjl
/* 4Gbit DDP NAND Flash */
{ 0xEC, 0xAC, 4096, 64, 4, 2, 80, 0, 2, 8, BW_X08, 50, 350, 2000, 50},
{ 0xEC, 0xDC, 4096, 64, 4, 2, 80, 0, 2, 8, BW_X08, 50, 350, 2000, 50},
//{ 0xEC, 0xBC, 4096, 64, 4, 2, 80, 0, 2, 8, BW_X16, 50, 350, 2000, 50},
//{ 0xEC, 0xCC, 4096, 64, 4, 2, 80, 0, 2, 8, BW_X16, 50, 350, 2000, 50},
/* 2Gbit NAND Flash */
{ 0xEC, 0xAA, 2048, 64, 4, 1, 40, 0, 2, 8, BW_X08, 50, 350, 2000, 50},
{ 0xEC, 0xDA, 2048, 64, 4, 1, 40, 0, 2, 8, BW_X08, 50, 350, 2000, 50},
//{ 0xEC, 0xBA, 2048, 64, 4, 1, 40, 0, 2, 8, BW_X16, 50, 350, 2000, 50},
//{ 0xEC, 0xCA, 2048, 64, 4, 1, 40, 0, 2, 8, BW_X16, 50, 350, 2000, 50},
/* 2Gbit DDP NAND Flash */
{ 0xEC, 0xDA, 2048, 64, 4, 2, 40, 0, 2, 8, BW_X08, 50, 350, 2000, 50},
{ 0xEC, 0xAA, 2048, 64, 4, 2, 40, 0, 2, 8, BW_X08, 50, 350, 2000, 50},
//{ 0xEC, 0xBA, 2048, 64, 4, 2, 40, 0, 2, 8, BW_X16, 50, 350, 2000, 50},
//{ 0xEC, 0xCA, 2048, 64, 4, 2, 40, 0, 2, 8, BW_X16, 50, 350, 2000, 50},
/*1Gbit NAND Flash */
{ 0xEC, 0xA1, 1024, 64, 4, 1, 20, 0, 2, 8, BW_X08, 50, 350, 2000, 50},
{ 0xEC, 0xF1, 1024, 64, 4, 1, 20, 0, 2, 8, BW_X08, 50, 350, 2000, 50},
//{ 0xEC, 0xB1, 1024, 64, 4, 1, 20, 0, 2, 8, BW_X16, 50, 350, 2000, 50},
//{ 0xEC, 0xC1, 1024, 64, 4, 1, 20, 0, 2, 8, BW_X16, 50, 350, 2000, 50},
/* 1Gbit NAND Flash */
{ 0xEC, 0x79, 8192, 32, 1, 4,120, 5, 0, 6, BW_X08, 50, 350, 2000, 50},
{ 0xEC, 0x78, 8192, 32, 1, 4,120, 5, 0, 6, BW_X08, 50, 350, 2000, 50},
//{ 0xEC, 0x74, 8192, 32, 1, 4,120,11, 0, 6, BW_X16, 50, 350, 2000, 50},
//{ 0xEC, 0x72, 8192, 32, 1, 4,120,11, 0, 6, BW_X16, 50, 350, 2000, 50},
/* 512Mbit NAND Flash */
{ 0xEC, 0x76, 4096, 32, 1, 4, 70, 5, 0, 6, BW_X08, 50, 350, 2000, 50},
{ 0xEC, 0x36, 4096, 32, 1, 4, 70, 5, 0, 6, BW_X08, 50, 350, 2000, 50},
/* 512Mbit XP Card */
{ 0x98, 0x76, 4096, 32, 1, 4, 70, 5, 0, 6, BW_X08, 50, 350, 2000, 50},
{ 0x98, 0x79, 4096, 32, 1, 4, 70, 5, 0, 6, BW_X08, 50, 350, 2000, 50},
//{ 0xEC, 0x56, 4096, 32, 1, 4, 70,11, 0, 6, BW_X16, 50, 350, 2000, 50},
//{ 0xEC, 0x46, 4096, 32, 1, 4, 70,11, 0, 6, BW_X16, 50, 350, 2000, 50},
/* 256Mbit NAND Flash */
{ 0xEC, 0x75, 2048, 32, 1, 1, 35, 5, 0, 6, BW_X08, 50, 350, 2000, 50},
{ 0xEC, 0x35, 2048, 32, 1, 1, 35, 5, 0, 6, BW_X08, 50, 350, 2000, 50},
//{ 0xEC, 0x55, 2048, 32, 1, 1, 35,11, 0, 6, BW_X16, 50, 350, 2000, 50},
//{ 0xEC, 0x45, 2048, 32, 1, 1, 35,11, 0, 6, BW_X16, 50, 350, 2000, 50},
/* 128Mbit NAND Flash */
{ 0xEC, 0x73, 1024, 32, 1, 1, 20, 5, 0, 6, BW_X08, 50, 350, 2000, 50},
{ 0xEC, 0x33, 1024, 32, 1, 1, 20, 5, 0, 6, BW_X08, 50, 350, 2000, 50},
//{ 0xEC, 0x53, 1024, 32, 1, 1, 20,11, 0, 6, BW_X16, 50, 350, 2000, 50},
//{ 0xEC, 0x43, 1024, 32, 1, 1, 20,11, 0, 6, BW_X16, 50, 350, 2000, 50},
{ 0x00, 0x00, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
};
#endif _S3C6410_CFNAND_H
且看
[cpp]
/* 16Gbit DDP NAND Flash */
0xEC, 0xD5, 4096, 128, 8, 2,160, 0, 2, 8, BW_X08, 50, 350, 2000, 50}
这里就是使用的2G（16/8 bit=2byte） Nandflash K9GAG08U0D的一些参数配置，其中 0xEC, 0xD5表示的是Nandflash的ID号，总共有4096个block,每个block有128个page,每个page有8个sector
要支持4G（K9LBG08U0D） 的话，则加上下面的配置：
[cpp] view plaincopy
/* 32Gbit DDP NAND Flash */
{ 0xEC, 0xD7, 8192, 128, 8, 1,160, 0, 2, 8, BW_X08, 50, 350, 2000, 50},
在看nand.h文件之前，我们先来看一下fmd.cpp中引用的#include "s3c6410_nand.h"头文件：（该文件在C:\WINCE600\PLATFORM\COMMON\SRC\SOC\S3C6410_SEC_V1\OAL\INC\s3c6410_nand.h）
[cpp]
//
// Copyright （c） Microsoft Corporation. All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement （EULA） under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//------------------------------------------------------------------------------
//
// Header: s3c6410_nand.h
//
// Defines the NAND controller CPU register layout and definitions.
//
#ifndef __S3C6410_NAND_H
#define __S3C6410_NAND_H
#if __cplusplus
extern "C"
{
#endif
//------------------------------------------------------------------------------
// Type: S3C6410_NAND_REG
//
// NAND Flash controller register layout. This register bank is located
// by the constant CPU_BASE_REG_XX_NAND in the configuration file
// cpu_base_reg_cfg.h.
//
typedef struct
{
UINT32 NFCONF; //0x00 // configuration reg
UINT32 NFCONT; //0x04
UINT8 NFCMD; //0x08 // command set reg
UINT8 d0 ;
UINT8 NFADDR; //0x0C // address set reg
UINT8 d1 ;
UINT8 NFDATA; //0x10 // data reg
UINT8 d2 ;
UINT32 NFMECCD0; //0x14
UINT32 NFMECCD1; //0x18
UINT32 NFSECCD; //0x1C
UINT32 NFSBLK; //0x20
UINT32 NFEBLK; //0x24 // error correction code 2
UINT32 NFSTAT; //0x28 // operation status reg
UINT32 NFECCERR0; //0x2C
UINT32 NFECCERR1; //0x30
UINT32 NFMECC0; //0x34 // error correction code 0
UINT32 NFMECC1; //0x38 // error correction code 1
UINT32 NFSECC; //0x3C
UINT32 NFMLCBITPT; //0x40
} S3C6410_NAND_REG, *PS3C6410_NAND_REG;
#if __cplusplus
}
#endif
#endif
注意到了麽？这个跟文档中的寄存器少了8bit ECC寄存器部分。
晕菜了吧，飞凌的这个2G 256M的BSP的Nandflash源码既然是这个样子，为什么还在那里号称8bit的ECC,还说开放源码。