mov r1, #0x23000000 @ start buffer register
orr r1, r1, #0x30000
orr r1, r1, #0xc800
#else //不执行
mov r1, =0x20000000 @ start buffer register
orr r1, r1, #0xc30000
orr r1, r1, #0xc800
#endif

sub r0, r1, #0x0400 @ start address1 register

ldr r2, [r1, #0x84] @ ecc bypass
orr r2, r2, #0x100
str r2, [r1, #0x84]

mov r3, #0x0 @ DFS, FBA
str r3, [r0, #0x00]
str r3, [r0, #0x04] @ select dataram for DDP as 0

mov r4, #0x104 @ interrupt register
mov r5, #0x0002 @ FPA, FSA
mov r6, #0x0800 @ BSA

onenand_bl1_load:
str r5, [r0, #0x1c] @ save FPA, FSA
orr r6, r6, #0x02 @ BSC
str r6, [r1, #0x00] @ save BSA, BSC
str r3, [r1, r4] @ clear interrupt
str r3, [r1, #0x80] @ write load command

mov r7, #0x100 @ need small delay

onenand_wait_loop1:
subs r7, r7, #0x1
bne onenand_wait_loop1

add r5, r5, #0x2 @ next FPA, FSA
sub r6, r6, #0x2
add r6, r6, #0x200 @ next BSA
cmp r5, #0x8
bne onenand_bl1_load
#endif

/*
* Go setup Memory and board specific bits prior to relocation.
*/
bl lowlevel_init /* go setup pll,mux,memory */

/* when we already run in ram, we don't need to relocate U-Boot.
* and actually, memory controller must be configured before U-Boot
* is running in ram.
*/

ldr r0, =0xff000fff

bic r1, pc, r0 /* r0 <- current base addr of code */
ldr r2, _TEXT_BASE /* r1 <- original base addr in ram */
bic r2, r2, r0 /* r0 <- current base addr of code */
cmp r1, r2 /* compare r0, r1 */
beq after_copy /* r0 == r1 then skip flash copy */
//使用nandflash，此处忽略
#ifdef CONFIG_BOOT_NOR /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
ldr r1, _TEXT_PHY_BASE /* r1 <- destination */
ldr r2, _armboot_start
ldr r3, _bss_start
sub r2, r3, r2 /* r2 <- size of armboot */
add r2, r0, r2 /* r2 <- source end address */

nor_copy_loop:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end addreee [r2] */
ble nor_copy_loop
b after_copy
#endif
//从Nandflash启动，执行此处代码
#ifdef CONFIG_BOOT_NAND
mov r0, #0x1000
bl copy_from_nand
#endif

#ifdef CONFIG_BOOT_MOVINAND
ldr sp, _TEXT_PHY_BASE
bl movi_bl2_copy
b after_copy
#endif
//使用nandflash，此处忽略
#ifdef CONFIG_BOOT_ONENAND
ldr sp, =0x50000000 @ temporary stack
//设置地址并分配空间
#ifdef CONFIG_S3C6400
mov r1, =0x20000000 @ start buffer register
orr r1, r1, #0xc30000
orr r1, r1, #0xc800
#else
mov r1, #0x23000000 @ start buffer register
orr r1, r1, #0x30000
orr r1, r1, #0xc800
#endif

ldr r2, [r1, #0x84] @ ecc bypass
orr r2, r2, #0x100
str r2, [r1, #0x84]

sub r0, r1, #0x0400 @ start address1 register

str r3, [r0, #0x00]
str r3, [r0, #0x04] @ select dataram for DDP as 0

mov r4, #0x104 @ interrupt register

mov r6, #0x0c00 @ fixed dataram1 sector number
str r6, [r1, #0x00]

mov r3, #0x0 @ DFS, FBA
mov r5, #0x0000 @ FPA, FSA
ldr r9, =CFG_PHY_UBOOT_BASE @ destination

onenand_bl2_load:
str r3, [r0, #0x00] @ save DFS, FBA
str r5, [r0, #0x1c] @ save FPA, FSA

mov r7, #0x0 @ clear interrupt
str r7, [r1, r4]
str r7, [r1, #0x80] @ write load command

mov r8, #0x1000
onenand_wait_loop2:
subs r8, r8, #0x1
bne onenand_wait_loop2

onenand_wait_int: @ wait INT and RI
ldr r7, [r1, r4]
mov r8, #0x8000
orr r8, r8, #0x80
tst r7, r8
beq onenand_wait_int

mov r7, #0x0 @ clear interrupt
str r7, [r1, r4]

mov r8, #0xc00 @ source address (dataram1)
mov r10, #0x40 @ copy loop count (64 = 2048 / 32)