1 `timescale 1ns/1ns
2 `define clk_period 50
3 module parallel_to_serial_test;
4 reg rst,clk;
5 reg [7:0]data,addr;
6 wire ack,sda;
7 wire [2:0]state; //main status,
8 wire [4:0]sh8out_state;
9
10 initial
11 begin
12 clk=0;
13 rst=1;
14 data=0;
15 addr=0;
16 #(2*`clk_period) rst=0;
17 #(2*`clk_period) rst=1;
18 #(100*`clk_period) $stop;
19 end
20
21 always #50 clk=~clk;
22
23
24
25 always @(posedge clk)
26 begin data=data+1; addr=addr+1; end
27
28 parallel_to_serial m(
29 .rst(rst),
30 .clk(clk),
31 .addr(addr),
32 .data(data),
33 .sda(sda),
34 .ack(ack)
35 );
36
37 assign state=m.state;
38 assign sh8out_state=m.sh8out_state;
39 endmodule