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-----------------------
68 //FSM step1
69 always @(posedge clk or negedge rst_n)begin
70 if(rst_n == 1'b0)begin
71 pre_state <= IDLE;
72 end
73 else begin
74 pre_state <= next_state;
75 end
76 end
77
78 //FSM step2
79 always @(*)begin
80 case(pre_state)
81 IDLE:begin
82 if(tran_en == 1'b1)
83 next_state = SHIFT;
84 else
85 next_state = IDLE;
86 end
87 SHIFT:begin
88 if(shift_cnt == SHIFT_DEPTH + 1)
89 next_state = DONE;
90 else
91 next_state = SHIFT;
92 end
93 DONE:begin
94 next_state = IDLE;
95 end
96 default:next_state = IDLE;
97 endcase
98 end
99
100 //FSM step3
101 always @(posedge clk or negedge rst_n)begin
102 if(rst_n == 1'b0)begin
103 thou_reg <= 4'b0;
104 hund_reg <= 4'b0;
105 tens_reg <= 4'b0;
106 unit_reg <= 4'b0;
107 tran_done <= 1'b0;
108 shift_cnt <= 'd0;
109 data_reg <= 'd0;
110 end
111 else begin
112 case(next_state)
113 IDLE:begin
114 thou_reg <= 4'b0;
115 hund_reg <= 4'b0;
116 tens_reg <= 4'b0;
117 unit_reg <= 4'b0;
118 tran_done <= 1'b0;
119 shift_cnt <= 'd0;
120 data_reg <= data_in;
121 end
122 SHIFT:begin
123 if(shift_cnt == SHIFT_DEPTH + 1)
124 shift_cnt <= 'd0;
125 else begin
126 shift_cnt <= shift_cnt + 1'b1;
127 data_reg <= data_reg << 1;
128 unit_reg <= {unit_tmp[2:0], data_reg[16]};
129 tens_reg <= {tens_tmp[2:0], unit_tmp[3]};
130 hund_reg <= {hund_tmp[2:0], tens_tmp[3]};
131 thou_reg <= {thou_tmp[2:0], hund_tmp[3]};
132 end
133 end
134 DONE:begin
135 tran_done <= 1'b1;
136 end
137 default:begin
138 thou_reg <= thou_reg;
139 hund_reg <= hund_reg;
140 tens_reg <= tens_reg;
141 unit_reg <= unit_reg;
142 tran_done <= tran_done;
143 shift_cnt <= shift_cnt;
144 end
145 endcase
146 end
147 end
148 //-------------------------------------------------------
149 always @(posedge clk or negedge rst_n)begin
150 if(rst_n == 1'b0)begin
151 thou_out <= 'd0;
152 hund_out <= 'd0;
153 tens_out <= 'd0;
154 unit_out <= 'd0;
155 end
156 else if(tran_done == 1'b1)begin
157 thou_out <= thou_reg;
158 hund_out <= hund_reg;
159 tens_out <= tens_reg;
160 unit_out <= unit_reg;
161 end
162 else begin
163 thou_out <= thou_out;
164 hund_out <= hund_out;
165 tens_out <= tens_out;
166 unit_out <= unit_out;
167 end
168 end
169
170
171 //-------------------------------------------------------
172 assign thou_tmp = (thou_reg > 4'd4)? (thou_reg + 2'd3) : thou_reg;
173 assign hund_tmp = (hund_reg > 4'd4)? (hund_reg + 2'd3) : hund_reg;
174 assign tens_tmp = (tens_reg > 4'd4)? (tens_reg + 2'd3) : tens_reg;
175 assign unit_tmp = (unit_reg > 4'd4)? (unit_reg + 2'd3) : unit_reg;
176
177 assign thou_data = thou_out;
178 assign hund_data = hund_out;
179 assign tens_data = tens_out;
180 assign unit_data = unit_out;
181
182
183 endmodule
Bin_BCD
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知乎ID：NingHeChuan
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原文地址：https://www.cnblogs.com/ninghechuan/p/9464037.html
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