{"rsdb":{"rid":"373490","subhead":"","postdate":"0","aid":"262030","fid":"92","uid":"1","topic":"1","content":"
\n

\u4e00\u3001\u524d\u8a00<\/strong><\/span><\/p> \n

\u3000\u3000\u5e94\u8058IC\u524d\u7aef\u76f8\u5173\u5c97\u4f4d\u65f6\uff0cFIFO\u662f\u6700\u5e38\u8003\u4e5f\u662f\u6700\u57fa\u672c\u7684\u9898\u76ee\u3002FIFO\u7ecf\u5e38\u7528\u4e8e\u6570\u636e\u7f13\u5b58\u3001\u4f4d\u5bbd\u8f6c\u6362\u3001\u5f02\u6b65\u65f6\u949f\u57df\u5904\u7406\u3002\u968f\u7740\u82af\u7247\u89c4\u6a21\u7684\u5feb\u901f\u589e\u957f\uff0c\u7075\u6d3b\u7684system verilog\u6210\u4e3a\u8bbe\u8ba1\/\u9a8c\u8bc1\u4eba\u5458\u7684\u57fa\u672c\u529f\u3002\u672c\u6587\u4ece\u7b80\u6613\u7248\u7684\u540c\u6b65FIFO\u5f00\u59cb\uff0c\u719f\u6089IP\u8bbe\u8ba1\u4e0e\u9a8c\u8bc1\u7684\u57fa\u7840\u6280\u80fd\u3002<\/span><\/p> \n

\u4e8c\u3001IP\u8bbe\u8ba1<\/span><\/strong><\/p> \n

\u3000\u3000FIFO\u8fd9\u4e00IP\u6838\u5df2\u7ecf\u76f8\u5f53\u6210\u719f\uff0c\u56e0\u6b64\u7f51\u4e0a\u8d44\u6599\u4e5f\u662f\u4e00\u6293\u4e00\u5927\u628a\u3002\u5176\u4e2d\u7b14\u8005\u8ba4\u4e3a\u8f83\u597d\u7684\u4e00\u4e2a\u5728\u6587\u672b\u9644\u5f55\u4e2d\uff0c\u9700\u8981\u8be6\u7ec6\u4e86\u89e3FIFO\u5de5\u4f5c\u539f\u7406\u7684\u670b\u53cb\u53ef\u4ee5\u4ed4\u7ec6\u770b\u770b\u3002\u8fd9\u91cc\u7b80\u5355\u4ecb\u7ecd\u4e0b\u672c\u6587\u8bbe\u8ba1FIFO\u7684\u539f\u7406\u4e0e\u7ed3\u6784\u3002FIFO\u7684\u5185\u90e8\u5b58\u50a8\u5355\u5143\u662f\u5e38\u89c1\u7684\u53cc\u53e3RAM\uff0c\u8fd9\u4e2aIP\u7684\u7cbe\u9ad3\u5728\u4e8e\u8bfb\u5199\u5730\u5740\u7684\u5bf9\u5916\u5c4f\u853d\u4e0e\u81ea\u52a8\u7ba1\u7406\u3002\u907f\u514d\u5199\u6ee1\u3001\u8bfb\u7a7a\u81f3\u5173\u91cd\u8981\u3002<\/em><\/strong>\u672c\u6587\u8bbe\u8ba1\u7684FIFO\u9876\u5c42\u4f8b\u5316\u53cc\u53e3RAM\u548cFIFO\u63a7\u5236\u4e24\u5927\u6a21\u5757\uff1a\u524d\u8005\u4ec5\u4f5c\u4e3a\u5b58\u50a8\u5355\u5143\u54cd\u5e94\u8bfb\u5199\u4fe1\u53f7\uff0c\u540e\u8005\u6839\u636e\u8bfb\u5199\u8ba1\u6570\u5668\u4ea7\u751f\u8bfb\u5199\u6307\u9488\u548c\u91cd\u8981\u7684\u7a7a\u6ee1\u6307\u793a\u4fe1\u53f7\u3002<\/span><\/p> \n

\u3000\u3000\u4ee3\u7801\u5982\u4e0b\uff1a<\/span><\/p> \n

\u5b58\u50a8\u6a21\u5757\uff1a<\/span><\/p> \n

\n \"\"\n \"\" \n
\n 
 1<\/span> `timescale 1ns\/1ps\r\n<\/span> 2<\/span> module<\/span> dpram\r\n<\/span> 3<\/span> #(parameter<\/span> D_W=8<\/span>,\r\n<\/span> 4<\/span>             A_W=8<\/span>)\r\n<\/span> 5<\/span> (\r\n<\/span> 6<\/span>   input<\/span>                   clk,\r\n<\/span> 7<\/span>   input<\/span>                   rst_n,\r\n<\/span> 8<\/span>   \/\/<\/span>write ports<\/span>\r\n 9<\/span>   input<\/span>                   wr_en,\r\n<\/span>10<\/span>   input<\/span>       [D_W-1<\/span>:0<\/span>]   wr_data,\r\n<\/span>11<\/span>   input<\/span>       [A_W-1<\/span>:0<\/span>]   wr_addr,\r\n<\/span>12<\/span>   \/\/<\/span>read ports<\/span>\r\n13<\/span>   input<\/span>                   rd_en,\r\n<\/span>14<\/span>   input<\/span>       [A_W-1<\/span>:0<\/span>]   rd_addr,\r\n<\/span>15<\/span>   output<\/span> reg<\/span>  [D_W-1<\/span>:0<\/span>]   rd_data\r\n<\/span>16<\/span> );\r\n<\/span>17<\/span> \/\/<\/span>RAM<\/span>\r\n18<\/span> reg<\/span> [D_W-1<\/span>:0<\/span>] memory [0<\/span>:2<\/span>**A_W-1<\/span>];\r\n<\/span>19<\/span> \r\n20<\/span> \/\/<\/span>write operation<\/span>\r\n21<\/span> always<\/span>@(posedge<\/span> clk)begin<\/span>\r\n22<\/span>   if<\/span>(wr_en)begin<\/span>\r\n23<\/span>     memory[wr_addr] <= wr_data;\r\n<\/span>24<\/span>   end<\/span>\r\n25<\/span> end<\/span>\r\n26<\/span> \r\n27<\/span> \/\/<\/span>read operation<\/span>\r\n28<\/span> always<\/span>@(posedge<\/span> clk or<\/span> negedge<\/span> rst_n)begin<\/span>\r\n29<\/span>   if<\/span>(~rst_n)\r\n<\/span>30<\/span>     rd_data <= 0<\/span>;\r\n<\/span>31<\/span>   else<\/span> if<\/span>(rd_en)begin<\/span>\r\n32<\/span>     rd_data <= memory[rd_addr];\r\n<\/span>33<\/span>   end<\/span>\r\n34<\/span>   else<\/span> if<\/span>(rd_addr == 1<\/span>)\r\n<\/span>35<\/span>     rd_data <= memory[0<\/span>];\r\n<\/span>36<\/span> end<\/span>\r\n37<\/span> \r\n38<\/span> endmodule<\/span><\/pre> \n  <\/div> \n  dpram<\/span>\n <\/div> \n 
FIFO\u63a7\u5236\u6a21\u5757\uff1a<\/span><\/p> \n 
\n  \"\"\n  \"\" \n  
 \n   
 1<\/span> `timescale 1ns\/1ps\r\n<\/span> 2<\/span> module<\/span> fifo_ctrl\r\n<\/span> 3<\/span> #(parameter<\/span> A_W = 8<\/span>,\r\n<\/span> 4<\/span>   parameter<\/span> [0<\/span>:0<\/span>] MODE = 0<\/span>\/\/<\/span>0- standard read 1- first word fall through<\/span>\r\n 5<\/span> )\r\n<\/span> 6<\/span> (\r\n<\/span> 7<\/span>   input<\/span> clk,\r\n<\/span> 8<\/span>   input<\/span> rst_n,\r\n<\/span> 9<\/span> \r\n10<\/span>   output<\/span> [A_W-1<\/span>:0<\/span>] wr_addr,\r\n<\/span>11<\/span>   output<\/span> [A_W-1<\/span>:0<\/span>] rd_addr,\r\n<\/span>12<\/span> \r\n13<\/span>   output<\/span> empty,\r\n<\/span>14<\/span>   output<\/span> full,\r\n<\/span>15<\/span>   input<\/span> wr_en,\r\n<\/span>16<\/span>   input<\/span> rd_en\r\n<\/span>17<\/span> );\r\n<\/span>18<\/span> localparam<\/span> MAX_CNT = 2<\/span>**A_W;\r\n<\/span>19<\/span> localparam<\/span> FD_W = A_W;\r\n<\/span>20<\/span> \r\n21<\/span> function<\/span> [FD_W-1<\/span>:0<\/span>] abs;\r\n<\/span>22<\/span>   input<\/span> signed<\/span> [FD_W-1<\/span>:0<\/span>] data;\r\n<\/span>23<\/span>   begin<\/span>\r\n24<\/span>     assign<\/span> abs = data >= 0<\/span> ? data : -data;\r\n<\/span>25<\/span>   end<\/span>\r\n26<\/span> endfunction<\/span>\r\n27<\/span> \r\n28<\/span> reg<\/span> [A_W-1<\/span>:0<\/span>] wr_cnt;\r\n<\/span>29<\/span> wire<\/span> add_wr_cnt,end_wr_cnt;\r\n<\/span>30<\/span> reg<\/span> wr_flag;\r\n<\/span>31<\/span> reg<\/span> [A_W-1<\/span>:0<\/span>] rd_cnt;\r\n<\/span>32<\/span> wire<\/span> add_rd_cnt,end_rd_cnt;\r\n<\/span>33<\/span> reg<\/span> rd_flag;\r\n<\/span>34<\/span> wire<\/span> [A_W+1<\/span>-1<\/span>:0<\/span>] wr_ptr,rd_ptr;\r\n<\/span>35<\/span> \r\n36<\/span> always<\/span>@(posedge<\/span> clk or<\/span> negedge<\/span> rst_n)begin<\/span>\r\n37<\/span>   if<\/span>(~rst_n)begin<\/span>\r\n38<\/span>     wr_cnt <= 0<\/span>;\r\n<\/span>39<\/span>   end<\/span>\r\n40<\/span>   else<\/span> if<\/span>(add_wr_cnt)begin<\/span>\r\n41<\/span>     if<\/span>(end_wr_cnt)\r\n<\/span>42<\/span>       wr_cnt <= 0<\/span>;\r\n<\/span>43<\/span>     else<\/span>\r\n44<\/span>       wr_cnt <= wr_cnt + 1<\/span>'<\/span>b1;<\/span>\r\n45<\/span>   end<\/span>\r\n46<\/span> end<\/span>\r\n47<\/span> \r\n48<\/span> assign<\/span> add_wr_cnt =  wr_en & ~full;\r\n<\/span>49<\/span> assign<\/span> end_wr_cnt = add_wr_cnt && wr_cnt == MAX_CNT - 1<\/span>;\r\n<\/span>50<\/span> \r\n51<\/span> always<\/span>@(posedge<\/span> clk or<\/span> negedge<\/span> rst_n)begin<\/span>\r\n52<\/span>   if<\/span>(~rst_n)begin<\/span>\r\n53<\/span>     wr_flag <= 0<\/span>;\r\n<\/span>54<\/span>   end<\/span>\r\n55<\/span>   else<\/span> if<\/span>(end_wr_cnt)begin<\/span>\r\n56<\/span>     wr_flag <= ~wr_flag;\r\n<\/span>57<\/span>   end<\/span>\r\n58<\/span> end<\/span>\r\n59<\/span> \r\n60<\/span> always<\/span>@(posedge<\/span> clk or<\/span> negedge<\/span> rst_n)begin<\/span>\r\n61<\/span>   if<\/span>(~rst_n)begin<\/span>\r\n62<\/span>     rd_cnt <= 0<\/span>;\r\n<\/span>63<\/span>   end<\/span>\r\n64<\/span>   else<\/span> if<\/span>(add_rd_cnt)begin<\/span>\r\n65<\/span>     if<\/span>(end_rd_cnt)\r\n<\/span>66<\/span>       rd_cnt <= 0<\/span>;\r\n<\/span>67<\/span>     else<\/span>\r\n68<\/span>       rd_cnt <= rd_cnt + 1<\/span>'<\/span>b1;<\/span>\r\n69<\/span>   end<\/span>\r\n70<\/span> end<\/span>\r\n71<\/span> \r\n72<\/span> assign<\/span> add_rd_cnt =  rd_en & ~empty;\r\n<\/span>73<\/span> assign<\/span> end_rd_cnt = add_rd_cnt && rd_cnt ==  MAX_CNT - 1<\/span>;\r\n<\/span>74<\/span> \r\n75<\/span> always<\/span>@(posedge<\/span> clk or<\/span> negedge<\/span> rst_n)begin<\/span>\r\n76<\/span>   if<\/span>(~rst_n)begin<\/span>\r\n77<\/span>     rd_flag <= 0<\/span>;\r\n<\/span>78<\/span>   end<\/span>\r\n79<\/span>   else<\/span> if<\/span>(end_rd_cnt)begin<\/span>\r\n80<\/span>     rd_flag <= ~rd_flag;\r\n<\/span>81<\/span>   end<\/span>\r\n82<\/span> end<\/span>\r\n83<\/span> \r\n84<\/span> assign<\/span> wr_ptr = {wr_flag,wr_cnt};\r\n<\/span>85<\/span> assign<\/span> rd_ptr = {rd_flag,rd_cnt};\r\n<\/span>86<\/span> \r\n87<\/span> assign<\/span> wr_addr = wr_cnt;\r\n<\/span>88<\/span> assign<\/span> rd_addr = rd_cnt + MODE;\r\n<\/span>89<\/span> \r\n90<\/span> assign<\/span> empty = wr_ptr == rd_ptr;\r\n<\/span>91<\/span> assign<\/span> full = (abs(wr_ptr[A_W-1<\/span>:0<\/span>] - rd_ptr[A_W-1<\/span>:0<\/span>]) < 1<\/span>) && (wr_ptr[A_W] != rd_ptr[A_W]);\r\n<\/span>92<\/span> \r\n93<\/span> endmodule<\/span><\/pre> \n  <\/div> \n  fifo_ctrl<\/span>\n <\/div> \n 
\u540c\u6b65FIFO\u9876\u5c42\uff1a<\/span><\/p> \n 
\n  \"\"\n  \"\" \n  
 \n   
 1<\/span> `timescale 1ns\/1ps\r\n<\/span> 2<\/span> module<\/span> fifo_sync\r\n<\/span> 3<\/span> #(parameter<\/span> D_W = 8<\/span>,\r\n<\/span> 4<\/span>             LOG_2_DEPTH = 8<\/span>,\/\/<\/span>2^8 = 256<\/span>\r\n 5<\/span>   parameter","orderid":"0","title":"\u540c\u6b65FIFO design and IP level verification(\u4e00)","smalltitle":"","mid":"0","fname":"Verilog","special_id":"0","bak_id":"0","info":"0","hits":"309","pages":"4","comments":"0","posttime":"2019-09-23 11:16:56","list":"1569208616","username":"admin","author":"","copyfrom":"","copyfromurl":"","titlecolor":"","fonttype":"0","titleicon":"0","picurl":"https:\/\/www.cppentry.com\/upload_files\/","ispic":"0","yz":"1","yzer":"","yztime":"0","levels":"0","levelstime":"0","keywords":"\u540c\u6b65<\/A> FIFO<\/A> design<\/A> and<\/A> level<\/A> verification<\/A>","jumpurl":"","iframeurl":"","style":"","template":"a:3:{s:4:\"head\";s:0:\"\";s:4:\"foot\";s:0:\"\";s:8:\"bencandy\";s:0:\"\";}","target":"0","ip":"14.17.22.33","lastfid":"0","money":"0","buyuser":"","passwd":"","allowdown":"","allowview":"","editer":"","edittime":"0","begintime":"0","endtime":"0","description":"\u540c\u6b65FIFO design and IP level verification","lastview":"1714833685","digg_num":"0","digg_time":"0","forbidcomment":"0","ifvote":"0","heart":"","htmlname":"","city_id":"0"},"page":"1"}