在验证verilog逻辑模块功能时候，我们可以从文件中读入激励，便于大规模的验证。文件中的数据我们可以用c++编写程序产生。

第一种读入文件的方法是用系统函数：$readmemb, readmemh, 第一个函数是读入二进制的字符串，第二个是读入16进制的字符串。

我们准备两个文本文件x1.txt

1111
1010
1110
0001

y1.txt

1101
0101
1010
0001

我们验证一个四位的加法器

加法器verilog代码如下：

module adder4(cout, sum, ina, inb, cin,clk);
output [3:0] sum;
output cout;
input [3:0] ina, inb;
input cin,clk;
reg[3:0] tempa, tempb, sum;
reg cout;
reg tempc;

always @(posedge clk)
begin
	tempa = ina;
	tempb = inb;
	tempc = cin;
end

always @(posedge clk)
begin
 {cout, sum} = tempa+ tempb + tempc;
end
endmodule

testbench代码如下，我们用readmemb函数读入激励，并在for循环中赋值给ina，inb

`timescale 1ns/1ns
 `include "adder4.v"

module adder_rw_tb;
reg[3:0] ina,inb;
reg cin;
reg clk = 0;
 wire[3:0] sum;
 wire cout;
reg[3:0] inam[0:3];
reg[3:0] inbm[0:3];
 integer i;
 always #10 clk =~ clk;

initial
 begin
     $readmemb("x1.txt",inam);
     $readmemb("y1.txt",inbm);
     for(i=0;i<4;i=i+1)
     begin
          #20 ina = inam[i];
              inb = inbm[i];
     end
 end

initial
 begin
     cin=0;
     repeat(2)
     #200 cin = {$random} % 16;
 end

adder4 adder4_0(
            .clk(clk),
            .sum(sum),
            .cout(cout),
            .ina(ina),
            .inb(inb),
            .cin(cin)
        );
 initial
 begin
     $monitor($time,,,"%b + %b + %b = {%b,%b}", ina, inb, cin,cout,sum);
     #400 $finish;
 end

initial
 begin
      $dumpfile("dump.vcd");
      $dumpvars;
 end
endmodule

用vcs编译后，run simv

Contains Synopsys proprietary information.
Compiler version M-2017.03-SP2-11; Runtime version M-2017.03-SP2-11;  Dec 21 19:34 2018
                    0  xxxx + xxxx + 0 = {x,xxxx}
                   20  1111 + 1101 + 0 = {x,xxxx}
                   30  1111 + 1101 + 0 = {1,1100}
                   40  1010 + 0101 + 0 = {1,1100}
                   50  1010 + 0101 + 0 = {0,1111}
                   60  1110 + 1010 + 0 = {0,1111}
                   70  1110 + 1010 + 0 = {1,1000}
                   80  0001 + 0001 + 0 = {1,1000}
                   90  0001 + 0001 + 0 = {0,0010}
$finish called from file "adder_rw_tb.v", line 44.
$finish at simulation time                  400
            V C S   S i m u l a t i o n   R e p o r t

在verdi中装入dump.vcd,波形如下：

修改testbench代码，用fdisplay把输出写到文件里面。

`timescale 1ns/1ns
`include "adder4.v&