VL50 简易秒表

`timescale 1ns/1ns

module count_module(
    input clk,
    input rst_n,

    output reg [5:0]second,
    output reg [5:0]minute
    );
    
    always@(posedge clk or negedge rst_n)
    begin
        if(~rst_n)
            second <= 'd0;
        else if(minute == 60)
            second <= second;
        else
            second <= (second<60)?second + 1:1;
    end
    
    always@(posedge clk or negedge rst_n)
    begin
        if(~rst_n)
            minute <= 'd0;
        else if(second == 60)
            minute <= minute + 1;
    end
    
endmodule

VL51 可置位计数器

狗屎一样的题目，不解释。

`timescale 1ns/1ns

module count_module(
    input clk,
    input rst_n,
    input set,
    input [3:0] set_num,
    output reg [3:0]number,
    output reg zero
    );
    reg [3:0]num;
    always@(posedge clk or negedge rst_n)
    begin
        if(~rst_n)
            num <= 'd0;
        else if(set)
            num <= set_num;
        else
            num <= num + 1;
    end

    always@(posedge clk or negedge rst_n)
    begin
        if(~rst_n)
            number <= 'd0;
        else 
            number <= num;
    end

    always@(posedge clk or negedge rst_n)
    begin
        if(~rst_n)
            zero <= 0;
        else if(num==0)
            zero <= 1;
        else 
            zero <= 0;
    end
endmodule

VL52 加减计数器

根据上一道题改一下就好了。

`timescale 1ns/1ns

module count_module(
    input clk,
    input rst_n,
    input mode,
    output reg [3:0]number,
    output reg zero
    );
    reg [3:0]num;
    always@(posedge clk or negedge rst_n)
    begin
        if(~rst_n)
            num <= 'd0;
        else if(mode)
            num <= (num<9)?num + 1:0;
        else
            num <= (num>0)?num - 1:9;
    end

    always@(posedge clk or negedge rst_n)
    begin
        if(~rst_n)
            number <= 'd0;
        else 
            number <= num;
    end

    always@(posedge clk or negedge rst_n)
    begin
        if(~rst_n)
            zero <= 0;
        else if(num==0)
            zero <= 1;
        else 
            zero <= 0;
    end
endmodule

VL53 单端口RAM

这个enb交wen比较合适，使能enb应该同时是读和写的使能。

注意地址7位，深度是128。

`timescale 1ns/1ns

module RAM_1port(
    input clk,
    input rst,
    input enb,
    input [6:0]addr,
    input [3:0]w_data,
    output wire [3:0]r_data
);
//*************code***********//
reg [3:0]ram[0:127];
integer i;
always@(posedge clk or negedge rst)
begin
    if(~rst)begin
        for(i=0;i<128;i=i+1)
            ram[i] <= 'd0;
    end else begin
        if(enb)begin
            ram[addr] <= w_data;
        end
    end
end
assign r_data=enb?'d0:ram[addr];
//*************code***********//
endmodule

VL54 RAM的简单实现

读写分别写一个always即可。

`timescale 1ns/1ns
module ram_mod(
    input clk,
    input rst_n,
    
    input write_en,
    input [7:0]write_addr,
    input [3:0]write_data,
    
    input read_en,
    input [7:0]read_addr,
    output reg [3:0]read_data
);
reg [3:0]ram[0:7];
integer i;
always@(posedge clk or negedge rst_n)
begin
    if(~rst_n)begin
        for(i=0;i<8;i=i+1)
            ram[i] <= 'd0;
    end else begin
        if(write_en)begin
            ram[write_addr] <= write_data;
        end
    end
end
always@(posedge clk or negedge rst_n)
begin
    if(~rst_n)begin
        read_data <= 'd0;
    end else begin
        if(read_en)begin
            read_data <= ram[read_addr];
        end
    end
end    
endmodule

 VL55 Johnson Counter

网上搜了一下约翰逊计数器原理就简单了，把最后一位的反，连到移位寄存器最开头就是扭环形计数器。

`timescale 1ns/1ns

module JC_counter(
   input                clk ,
   input                rst_n,
 
   output reg [3:0]     Q  
);
always@(posedge clk or negedge rst_n)
begin
    if(~rst_n)
        Q <= 'd0;
    else
        Q <= {~Q[0],Q[3:1]};
end
endmodule

VL56 流水线乘法器

把四个数相加拆分成两个数相加，从而实现简单的流水线。

`timescale 1ns/1ns

module multi_pipe#(
    parameter size = 4
)(
    input                         clk         ,   
    input                         rst_n        ,
    input    [size-1:0]            mul_a        ,
    input    [size-1:0]            mul_b        ,
 
     output    reg    [size*2-1:0]    mul_out        
);
wire [size*2-1:0]temp[0:size-1];
reg [size*2-1:0]adder[0:1];

genva