VL33 非整数倍数据位宽转换8to12

和上一题一样的，注意valid_out输出时加一个valid_in（其实32题也要加，不过不加仿真也能过）。

`timescale 1ns/1ns

module width_8to12(
    input                    clk         ,   
    input                   rst_n        ,
    input                      valid_in    ,
    input    [7:0]               data_in    ,
 
     output  reg               valid_out,
    output  reg [11:0]   data_out
);
reg [2:0]count;
always@(posedge clk or negedge rst_n)
begin
    if(~rst_n)
        count <= 0;
    else if(valid_in)
        count <= (count<2)?count + 1:0;
end
always@(posedge clk or negedge rst_n)
begin
    if(~rst_n)
        valid_out <= 0;
    else if(valid_in&&(count==1||count==2))
        valid_out <= 1;
    else
        valid_out <= 0;
end
reg [11:0]data_lock;
always@(posedge clk or negedge rst_n)
begin
    if(~rst_n)begin
        data_lock <= 0;
        data_out <= 0;
    end else if(valid_in)begin
        data_lock <= {data_lock[3:0],data_in};
        if(count == 1)
            data_out <= {data_lock[7:0],data_in[7:4]};
        else if(count == 2)
            data_out <= {data_lock[3:0],data_in};
    end
end
endmodule

VL34 整数倍数据位宽转换8to16

越做越简单了，整数倍位宽转换就非常轻松了。

`timescale 1ns/1ns

module width_8to16(
    input                    clk         ,   
    input                    rst_n        ,
    input                      valid_in    ,
    input       [7:0]           data_in    ,
 
     output    reg            valid_out,
    output   reg [15:0]    data_out
);
reg count;
always@(posedge clk or negedge rst_n)
begin
    if(~rst_n)
        count <= 0;
    else if(valid_in)
        count <= count + 1;
end
always@(posedge clk or negedge rst_n)
begin
    if(~rst_n)
        valid_out <= 0;
    else if(valid_in && count)
            valid_out <= 1;
    else
        valid_out <= 0;
end
reg [7:0]data_lock;
always@(posedge clk or negedge rst_n)
begin
    if(~rst_n)begin
        data_lock <= 0;
        data_out <= 0;
    end else if(valid_in)begin
        data_lock <= data_in;
        if(count == 1)
            data_out <= {data_lock,data_in};
    end
end
endmodule

VL35 状态机-非重叠的序列检测

也是一道比较简单的题，不过要注意是非重叠检测，用状态机比用移位寄存器更方便一点。

`timescale 1ns/1ns

module sequence_test1(
    input wire clk  ,
    input wire rst  ,
    input wire data ,
    output reg flag
);
//*************code***********//
reg [2:0]state,next_state;
localparam S0=0,S1=1,S2=2,S3=3,S4=4;
always@(posedge clk or negedge rst)
begin
    if(~rst)
        state <= S0;
    else
        state <= next_state;
end
always@(*)
begin
    case(state)
    S0:next_state = data ? S1 :S0;
    S1:next_state = data ? S1 :S2;
    S2:next_state = data ? S3 :S0;
    S3:next_state = data ? S4 :S2;
    S4:next_state = data ? S0 :S2;
    default:next_state = S0;
    endcase
end
always@(posedge clk or negedge rst)
begin
    if(~rst)
        flag <= 0;
    else if(state == S4 && data)
        flag <= 1;
    else 
        flag <= 0;
end
//*************code***********//
endmodule

VL36 状态机-重叠序列检测

重叠序列用移位寄存器肯定更方便，不过题目要求用状态机，同样也是注意状态跳变就行了。注意输出延后了一个周期，可以通过加一个状态来实现。

`timescale 1ns/1ns

module sequence_test2(
    input wire clk  ,
    input wire rst  ,
    input wire data ,
    output reg flag
);
//*************code***********//
reg [2:0]state,next_state;
localparam S0=0,S1=1,S2=2,S3=3,S4=4;
always@(posedge clk or negedge rst)
begin
    if(~rst)
        state <= S0;
    else
        state <= next_state;
end
always@(*)
begin
    case(state)
    S0:next_state = data ? S1 :S0;
    S1:next_state = data ? S1 :S2;
    S2:next_state = data ? S3 :S0;
    S3:next_state = data ? S4 :S2;
    S4:next_state = data ? S1 :S2;
    default:next_state = S0;
    endcase
end
always@(posedge clk or negedge rst)
begin
    if(~rst)
        flag <= 0;
    else if(state == S4)
        flag <= 1;
    else 
        flag <= 0;
end
//*************code***********//
endmodule

 VL37 时钟分频（偶数）

一眼行波计数器，不过输出定义的是wire，懒得再去改了。

我这里是组合逻辑输出，其实也