{"rsdb":{"rid":"395321","subhead":"","postdate":"0","aid":"272600","fid":"92","uid":"1","topic":"1","content":"
\n

\u7b80\u4ecb<\/h1> \n

\u6309\u952e<\/h3> \n

\u6309\u952e\u662f\u8f93\u5165\u8bbe\u5907\uff0c\u4e00\u822c\u6765\u8bf4\uff0c\u6309\u952e\u5728\u6ca1\u6709\u6309\u4e0b\u7684\u65f6\u5019\u662f\u9ad8\u7535\u5e73\uff1b\u5f53\u6309\u952e\u6309\u4e0b\u7684\u65f6\u5019\uff0c\u4e3a\u4f4e\u7535\u5e73\u3002<\/p> \n \n

\u5728DE2-70 User Manual<\/strong><\/em>\u4e2d<\/p> \n

\n

Each switch provides a high logic level (3.3 volts) when it is not pressed, and provides a low logic level (0 volts) when depressed. Since the pushbutton switches are debounced, they are appropriate for use as clock or reset inputs in a circuit.<\/p> \n <\/blockquote> \n

\u8fd9\u91cc\u4ecb\u7ecd\u5230\u4e86\u6309\u952e\u6296\u52a8\uff08Button Bouncing<\/strong>\uff09\u548c\u6309\u952e\u6d88\u6296\uff08Button Debouncing<\/strong>\uff09\u3002<\/p> \n \n

\u6309\u952e\u6d88\u6296<\/h3> \n

\u6309\u952e\u6d88\u6296\u901a\u5e38\u7684\u6309\u952e\u6240\u7528\u5f00\u5173\u4e3a\u673a\u68b0\u5f39\u6027\u5f00\u5173\uff0c\u5f53\u673a\u68b0\u89e6\u70b9\u65ad\u5f00\u3001\u95ed\u5408\u65f6\uff0c\u7531\u4e8e\u673a\u68b0\u89e6\u70b9\u7684\u5f39\u6027\u4f5c\u7528\uff0c\u4e00\u4e2a\u6309\u952e\u5f00\u5173\u5728\u95ed\u5408\u65f6\u4e0d\u4f1a\u9a6c\u4e0a\u7a33\u5b9a\u5730\u63a5\u901a\uff0c\u5728\u65ad\u5f00\u65f6\u4e5f\u4e0d\u4f1a\u4e00\u4e0b\u5b50\u65ad\u5f00\u3002\u56e0\u800c\u5728\u95ed\u5408\u53ca\u65ad\u5f00\u7684\u77ac\u95f4\u5747\u4f34\u968f\u6709\u4e00\u8fde\u4e32\u7684\u6296\u52a8\uff0c\u4e3a\u4e86\u4e0d\u4ea7\u751f\u8fd9\u79cd\u73b0\u8c61\u800c\u4f5c\u7684\u63aa\u65bd\u5c31\u662f\u6309\u952e\u6d88\u6296\u3002<\/p> \n

\u4e0a\u56fe\u63cf\u8ff0\u7684\u662f\u786c\u4ef6\u7684\u6309\u952e\u6d88\u6296\u3002\u53ef\u89c1\uff0c\u6d88\u6296\u540e\uff0c\u4e00\u6b21<\/strong>\u6309\u952e\uff0c\u53ea\u4ea7\u751f\u4e86\u4e00\u6b21<\/strong>\u7535\u5e73\u53d8\u5316\u3002<\/p> \n

\u8fd9\u5bf9\u6211\u4eec\u63a5\u4e0b\u6765\u5229\u7528\u6309\u952e\u610f\u4e49\u91cd\u5927\u3002<\/p> \n

\u7269\u7406\u6d88\u6296<\/h1> \n

\u7b80\u5355\u4ecb\u7ecd\u4e0b\u5b9e\u73b0\u4e0a\u56fe\u7684\u6d88\u6296\u3002<\/p> \n

\u7535\u5bb9\u6ee4\u6ce2<\/h3> \n

\u5c06\u7535\u5bb9\u5e76\u8054\u5728\u6309\u952e\u7684\u4e24\u7aef\uff0c\u5229\u7528\u7535\u5bb9\u7684\u653e\u7535\u7684\u5ef6\u65f6\u7279\u6027\u3002\u5c06\u4ea7\u751f\u6296\u52a8\u7684\u7535\u5e73\u901a\u8fc7\u7535\u5bb9\u5438\u6536\u6389\u3002\u4ece\u800c\u8fbe\u5230\u6d88\u6296\u7684\u4f5c\u7528\u3002<\/p> \n

\"\"<\/p> \n

RS\u89e6\u53d1\u5668<\/h3> \n

\u5229\u7528RS\u89e6\u53d1\u5668\u6765\u5438\u6536\u6309\u952e\u7684\u6296\u52a8\u3002\u4e00\u65e6\u6709\u952e\u6309\u4e0b\uff0c\u89e6\u53d1\u5668\u7acb\u5373\u7ffb\u8f6c\uff0c\u89e6\u7535\u7684\u6296\u52a8\u4fbf\u4e0d\u4f1a\u518d\u5bf9\u8f93\u51fa\u4ea7\u751f\u5f71\u54cd\u3002<\/p> \n

\"\"<\/p> \n

\u7a0b\u5e8f\u6d88\u6296<\/h1> \n

\u6309\u952e\u5728FPGA<\/strong>\u4e2d\u5fc5\u4e0d\u53ef\u5c11\uff0c\u6211\u4eec\u9700\u8981\u5229\u7528\u6309\u952e\u5bf9\u4e00\u4e9b\u53d8\u91cf\u8fdb\u884c\u7d2f\u52a0\u6216\u7d2f\u51cf\u3002\u6bd4\u5982\u9891\u7387\u3001\u5206\u6570\u7b49\u3002<\/p> \n

\u672a\u6d88\u6296<\/h3> \n

\u5728\u4e00\u5f00\u59cb\u7684\u5b66\u4e60\u4e2d\uff0c\u6211\u4eec\u53ef\u80fd\u53ea\u7528\u5230\u4e86\u5f00\u5173\uff08switch<\/strong>\uff09\uff0c\u7f16\u5199\u5f00\u5173\u63a7\u5236\u7684\u7a0b\u5e8f\u7c7b\u4f3c\u4e8e\u5c06\u5f00\u5173\u5f53\u4f5c\u4e00\u4e2a\u5e03\u5c14\uff08Boolean<\/strong>\uff09\u53d8\u91cf\u3002<\/p> \n

\u4f46\u662f\u6309\u952e\u4e0e\u5f00\u5173\u4e0d\u540c\uff0c\u4ee5\u4e0b\u9762\u8fd9\u6bb5\u4ee3\u7801\u4e3a\u4f8b\uff0c\u671f\u671b\u4f5c\u7528\u662f \u6309\u952e\u6309\u4e0b\u540e\uff0cLED\u706f\u72b6\u6001\u6539\u53d8<\/strong>\u3002<\/p> \n

module Test(\n    input       sys_clk,\n    input       rst_n,\n    input       key,\n    output  reg led\n);\n    always@(posedge sys_clk or negedge rst_n)\n    begin\n        if(rst_n == 1'b0) \n            led <= 1'b0;\n        else if(key == 1'b0)\n            led <= ~led;\n        else\n            led <= led;\n    end\nendmodule\n<\/code><\/pre> \n 

\u7136\u800c\uff0c\u4e0a\u677f\u6d4b\u8bd5\u53d1\u73b0\uff0cLED\u72b6\u6001\u706f\u4e00\u76f4\u5904\u4e8e\u4e0d\u4eae\u7684\u72b6\u6001\u3002<\/p> \n

\u5047\u8bbe\uff0c\u6211\u4eec\u7684\u65f6\u949f\u9891\u7387\u662f50MHz<\/strong>\uff0c\u90a3\u4e48\u5b83\u7684\u5468\u671f\u5c31\u662f20ns<\/strong>\u3002<\/p> \n

\u90a3\u4e48\uff0c\u5728\u4f60\u6309\u6309\u94ae\u7684\u5168\u8fc7\u7a0b\u4e2d\uff0c\u6309\u4e0b\u7684\u72b6\u6001\u6301\u7eed\u4e86\u591a\u957f\u65f6\u95f4\u5462\uff1f<\/p> \n

\u663e\u7136\uff0c\u8fdc\u5927\u4e8e20ns<\/strong>\uff0c\u6240\u4ee5LED\u4f1a\u591a\u6b21\u53d6\u53cd\u3002\u6240\u4ee5\u8fd9\u79cd\u7b80\u5355\u7c97\u66b4\u7684\u65b9\u6cd5\u662f\u4e0d\u9002\u5408\u6309\u952e\u7684\u3002<\/p> \n

\u6d88\u6296<\/h3> \n

\u6211\u4eec\u521a\u521a\u7684\u95ee\u9898\u662f\uff0c\u77ed\u65f6\u95f4\u5185\u91cd\u590d\u68c0\u6d4b<\/strong>\uff0c\u4ece\u800c\u591a\u6b21\u6267\u884c\u4e86\u6309\u952e\u540e\u7684\u884c\u4e3a\u3002<\/p> \n

\u53ef\u4ee5\u60f3\u5230\uff0c\u7ed9\u8fd9\u4e2a\u6309\u952e\u5b9a\u4e2a\u65f6<\/strong>\uff1a\u5f53\u6709\u6309\u952e\u6309\u4e0b\uff0c\u8ba1\u6570\u5668\u4e0d\u65ad\u81ea\u589e\uff0c\u82e5\u56e0\u4e3a\u6296\u52a8\uff0c\u5219\u8ba1\u6570\u5668\u4f1a\u6e05\u7a7a\uff0c\u91cd\u65b0\u8ba1\u6570\uff0c\u5f53\u4e0d\u6296\u52a8\u7684\u65f6\u5019\uff0c\u5c31\u4f1a\u8ba1\u6ee1\uff0c\u6b64\u65f6\u624d\u4f1a\u5224\u5b9a\u4e3a\u6309\u952e\u6309\u4e0b\u3002<\/p> \n

\u4ee3\u7801<\/p> \n

\/\/ \u5b9a\u65f6\u5668\u6d88\u9664\u6296\u52a8\nmodule key_filter(\n    input\twire            sys_clk,          \/\/ 50M\u65f6\u949f\n    input   wire         \tsys_rst_n,        \/\/ \u590d\u4f4d\u4fe1\u53f7\uff0c\u4f4e\u7535\u5e73\u6709\u6548\n    input   wire      \t\tkey,              \/\/ \u6309\u952e\u8f93\u5165\n\n    output \treg       \t\tkey_flag,         \/\/ \u6309\u952e\u4fe1\u53f7\u6709\u6548\u4fe1\u53f7\n\toutput \treg       \t\tkey_value         \/\/ \u6d88\u6296\u540e\u7684\u6309\u952e\u4fe1\u53f7  \n   );\n \n    reg [31:0] delay_cnt;\t\/\/ 32\u4f4d\u5b9a\u65f6\u5668\n\treg        key_reg; \n\nalways @(posedge sys_clk or negedge sys_rst_n) begin \n    if (!sys_rst_n) begin \n        key_reg   <= 1'b1;\n        delay_cnt <= 32'd0;\n    end\n    else begin\n        key_reg <= key;\n        if(key_reg != key)             \/\/ \u68c0\u6d4b\u5230\u6309\u952e\u72b6\u6001\u53d1\u751f\u53d8\u5316(\u6309\u4e0b \u6216 \u91ca\u653e)\n            delay_cnt <= 32'd1000000;  \/\/ \u8ba1\u6570\u5668\u88c5\u8f7d\u521d\u59cb\u503c\uff08\u8ba1\u6570\u65f6\u95f4\u4e3a20ms\uff09\n        else if(key_reg == key) begin  \/\/ \u6309\u952e\u72b6\u6001\u7a33\u5b9a\u65f6\uff0c\u8ba1\u6570\u5668\u9012\u51cf\uff0c\u5f00\u59cb20ms\u5012\u8ba1\u65f6\n            if(delay_cnt > 32'd0) \t   \/\/ \u4e0d\u7a33\u5b9a\u65f6\uff0c\u91cd\u65b0\u8ba1\u65f6\n                     delay_cnt <= delay_cnt - 1'b1;\n                 else\n                     delay_cnt <= delay_cnt;\n             end           \n    end   \nend\n\nalways @(posedge sys_clk or negedge sys_rst_n) begin \n    if (!sys_rst_n) begin \t\t\t   \/\/ \u590d\u4f4d\n        key_flag  <= 1'b0;\t\t\t   \/\/ \u65e0\u6548\n        key_value <= 1'b1;             \/\/ \u9ad8\u7535\u5e73\u4e3a\u672a\u6309\u4e0b\n    end\n    else begin\n        if(delay_cnt == 32'd1) begin   \/\/ \u6309\u952e\u7a33\u5b9a\u72b6\u6001\u7ef4\u6301\u4e8620ms\n            key_flag  <= 1'b1;         \/\/ \u6b64\u65f6\u6d88\u6296\u8fc7\u7a0b\u7ed3\u675f\uff0c\u4fe1\u53f7\u6709\u6548\n            key_value <= key;          \/\/ \u4fdd\u5b58\u6b64\u65f6\u6309\u952e\u4fe1\u53f7\n        end\t\t\t\t\t\t\t   \n        else begin\n            key_flag  <= 1'b0;\n            key_value <= key_value; \n        end  \n    end   \nend\n    \nendmodule \n<\/code><\/pre> \n 
\n

\u5982\u6b64\uff0c\u6211\u4eec\u518d\u91cd\u65b0\u5199\u4e0b\u521a\u521a\u7684\u672a\u6d88\u6296\u7a0b\u5e8f\u3002<\/p> \n

module Test(\n      input   \t    \tsys_clk,     \/\/ \u7cfb\u7edf\u65f6\u949f\n      input   \t    \trst_n,       \/\/ \u590d\u4f4d\u4fe1\u53f7\uff0c\u4f4e\u7535\u5e73\u6709\u6548\n      input       \t    key,\t     \/\/ \u6309\u952e\u4fe1\u53f7       \n\t  output    reg     led\t\t\t \/\/ LED\u706f\n  );\n  \nwire key_value;\nwire key_flag;\n\/\/ \u4f8b\u5316\nkey_filter\tkey_filter_inst(\n    .sys_clk\t\t(sys_clk),     \/\/ 50M\u65f6\u949f\n    .sys_rst_n\t\t(sys_rst_n),   \/\/ \u590d\u4f4d\u4fe1\u53f7\uff0c\u4f4e\u7535\u5e73\u6709\u6548\n    .key            (key),         \/\/ \u6309\u952e\u8f93\u5165)\n\n    .key_flag\t\t(key_flag),    \/\/ \u6309\u952e\u4fe1\u53f7\u6709\u6548\u4fe1\u53f7\n    .key_value      (key_value)    \/\/ \u6309\u952e\u6d88\u6296\u540e\u7684\u6570\u636e  \n);\nalways @ (posedge sys_clk or negedge sys_rst_n) begin\n    if(!sys_rst_n)\t\n\tbegin\n\t\tled <= 1'b0;\n\tend\n    else if(key_flag && (~key_value))  \/\/ \u6309\u952e\u662f\u5426\u6709\u6548\u6309\u4e0b\n\tbegin\t\t\t\t\t\t\n\t\t led  <= ~led;\n\tend\n    else\n    begin\n        led <= led;\n    end\nend\nendmodule \n\n<\/code><\/pre> \n 

\u6210\u529f\uff0c\u6309\u952e\u53ef\u4ee5\u63a7\u5236LED\u706f\u4eae\u4e0e\u7184\u706d\u3002\u4eff\u771f\u7565\u3002<\/p> \n

\u8fd9\u662f\u7b80\u5355\u7684\u8ba1\u65f6\u6d88\u6296\uff0c\u8bfb\u8005\u6709\u5174\u8da3\u53ef\u9605\u8bfb\u5b66\u4e60\u72b6\u6001\u673a\u7684\u65b9\u6cd5<\/a>\u3002<\/p> \n

\u53c2\u8003\u6587\u732e<\/h1> \n

[1] \u6309\u952e\u7684\u786c\u4ef6\u6d88\u6296\u7535\u8def\u539f\u7406\u8be6\u89e3<\/a><\/p> \n

[2] FPGA\u8981\u6309\u952e\u5b9e\u73b0\u56db\u4e2a\u6570\u7801\u7ba1\u52a0\u51cf\u8ba1\u6570\u600e\u4e48\u641e\uff1f<\/a><\/p> \n

[3] FPGA\u5b66\u4e60\u2014\u6309\u952e\u63a7\u5236<\/a><\/p> \n

[4] DE2-70 User Manual<\/em><\/p> \n<\/div>","orderid":"0","title":"FPGA\u6309\u952e\u6d88\u6296","smalltitle":"","mid":"0","fname":"Verilog","special_id":"0","bak_id":"0","info":"0","hits":"197","pages":"1","comments":"0","posttime":"2023-08-06 07:49:44","list":"1691279384","username":"admin","author":"","copyfrom":"","copyfromurl":"","titlecolor":"","fonttype":"0","titleicon":"0","picurl":"https:\/\/www.cppentry.com\/upload_files\/","ispic":"0","yz":"1","yzer":"","yztime":"0","levels":"0","levelstime":"0","keywords":"FPGA<\/A>","jumpurl":"","iframeurl":"","style":"","template":"a:3:{s:4:\"head\";s:0:\"\";s:4:\"foot\";s:0:\"\";s:8:\"bencandy\";s:0:\"\";}","target":"0","ip":"211.148.71.108","lastfid":"0","money":"0","buyuser":"","passwd":"","allowdown":"","allowview":"","editer":"","edittime":"0","begintime":"0","endtime":"0","description":"FPGA\u6309\u952e\u6d88\u6296","lastview":"1713291261","digg_num":"0","digg_time":"0","forbidcomment":"0","ifvote":"0","heart":"","htmlname":"","city_id":"0"},"page":"1"}