设为首页 加入收藏

TOP

lcd1602如何自定义汉字(verilog)(二)
2017-10-10 12:21:29 】 浏览:2505
Tags:lcd1602 如何 定义 汉字 verilog
sign write_flag = (cnt_500hz==TIME_500HZ - 1) ? 1'b1 : 1'b0 ; //set_function ,display off ,display clear ,entry mode set //---------------------------------------------------------------------- always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin c_state <= IDLE ; end else if(write_flag==1) begin c_state<= n_state ; end else c_state<=c_state ; end //-------------------------修改2 因为自定义一个汉字需要写8次地址并且给8次数据,所以用num和num1来控制。 reg [2:0]num,num1; always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin num<=0; end else if(c_state== CGRAM_ADDR&&write_flag) begin if(num==7) num<=0; else num<=num+8'b1; end else num<=num; end always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin num1<=0; end else if(c_state== CGRAM_DATA&&write_flag) begin if(num1==7) num1<=0; else num1<=num1+8'b1; end else num1<=num1; end //------------------------------------------------------------ always @(*)begin case (c_state) IDLE: n_state = SET_FUNCTION ; SET_FUNCTION: n_state = DISP_OFF ; DISP_OFF: n_state = DISP_CLEAR ; DISP_CLEAR: n_state = ENTRY_MODE ; ENTRY_MODE: n_state = DISP_ON ; DISP_ON : n_state = CGRAM_ADDR ; //------------------------------------------------ 修改3 当8个数据都写进相应地址里的时候,状态机才跳到ROW1_ADDR状态 CGRAM_ADDR: n_state = CGRAM_DATA ; // 8'hfe; CGRAM_DATA: if(num1==7) n_state = ROW1_ADDR; else n_state= CGRAM_ADDR; //------------------------------------------------ ROW1_ADDR: n_state = ROW1_0 ; ROW1_0: n_state = ROW1_1 ; ROW1_1: n_state = ROW1_2 ; ROW1_2: n_state = ROW1_3 ; ROW1_3: n_state = ROW1_4 ; ROW1_4: n_state = ROW1_5 ; ROW1_5: n_state = ROW1_6 ; ROW1_6: n_state = ROW1_7 ; ROW1_7: n_state = ROW1_8 ; ROW1_8: n_state = ROW1_9 ; ROW1_9: n_state = ROW1_A ; ROW1_A: n_state = ROW1_B ; ROW1_B: n_state = ROW1_C ; ROW1_C: n_state = ROW1_D ; ROW1_D: n_state = ROW1_E ; ROW1_E: n_state = ROW1_F ; ROW1_F: n_state = ROW2_ADDR ; ROW2_ADDR: n_state = ROW2_0 ; ROW2_0: n_state = ROW2_1 ; ROW2_1: n_state = ROW2_2 ; ROW2_2: n_state = ROW2_3 ; ROW2_3: n_state = ROW2_4 ; ROW2_4: n_state = ROW2_5 ; ROW2_5: n_state = ROW2_6 ; ROW2_6: n_state = ROW2_7 ; ROW2_7: n_state = ROW2_8 ; ROW2_8: n_state = ROW2_9 ; ROW2_9: n_state = ROW2_A ; ROW2_A: n_state = ROW2_B ; ROW2_B: n_state = ROW2_C ; ROW2_C: n_state = ROW2_D ; ROW2_D: n_state = ROW2_E ; ROW2_E: n_state = ROW2_F ; ROW2_F: n_state = ROW1_ADDR ; default: n_state = n_state ; endcase end assign lcd_rw = 0; always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin lcd_rs <= 0 ; //order or data 0: order 1:data end else if(write_flag == 1)begin if((n_state==SET_FUNCTION)||(n_state==DISP_OFF)|| (n_state==DISP_CLEAR)||(n_state==ENTRY_MODE)|| (n_state==DISP_ON ) ||(n_state==ROW1_ADDR)|| (n_state==ROW2_ADDR)||(n_state==CGRAM_ADDR))begin //修改4 lcd_rs<=0 ; end else begin lcd_rs<= 1; end end else begin lcd_rs<=lcd_rs; end end always @(posedge clk or negedge rst_n)begin if(rst_n==1'b0)begin lcd_data<=0 ; end else if(write_flag)begin case(n_state) IDLE: lcd_data <= 8'hxx; SET_FUNCTION: lcd_data <= 8'h38; //2*16 5*8 8位数据 DISP_OFF: lcd_data <= 8'h08; DISP_CLEAR: lcd_data <= 8'h01; ENT
首页 上一页 1 2 3 下一页 尾页 2/3/3
】【打印繁体】【投稿】【收藏】 【推荐】【举报】【评论】 【关闭】 【返回顶部
上一篇使用Synplify综合时保留logic 下一篇lcd1602如何自定义汉字(verilog)

最新文章

热门文章

Hot 文章

Python

C 语言

C++基础

大数据基础

linux编程基础

C/C++面试题目