end
endmodule
uart_byte_rx.v
`timescale 1ns / 1ps
module uart_byte_rx
# (
parameter RX_BAUD = 9600,
parameter CLK_FQC = 50_000_000,
parameter BAUD_CNT = CLK_FQC/RX_BAUD)
(
input Clk,
input Rst_n,
input Uart_rx,
output reg [7:0] Data,
output reg Rx_done
);
reg uart_rx_r;
reg uart_rx_rr;
reg receiv_begin;
reg receiv_flag;
reg [ 3:0] state;
reg [15:0] baud_cnt;
reg [ 3:0] sampel_cnt;
reg sampel_en;
reg sampel_ref;
reg [ 3:0] acc;
reg [ 3:0] bit_cnt;
always @(posedge Clk) begin
uart_rx_r <= Uart_rx;
uart_rx_rr <= uart_rx_r;
end
always @(posedge Clk or negedge Rst_n) begin
if(Rst_n == 0)
receiv_begin <= 0;
else if(state == 0 & uart_rx_rr & ~uart_rx_r)
receiv_begin <= 1'b1;
else
receiv_begin <= 0;
end
always @(posedge Clk or negedge Rst_n) begin
if(Rst_n == 0) begin
state <= 0;
sampel_ref <= 8'b0;
acc <= 8'b0;
Data <= 8'b0;
end
else case(state)
0:
if(receiv_begin == 1)
state <= 3'd1;
else
state <= 0;
1: begin
if(sampel_en == 1) begin
sampel_ref <= Uart_rx;
state <= 3'd2;
end
else
state <= 3'b1;
end
2: begin
acc <= acc + sampel_ref;
if(sampel_cnt == 7) begin
if(acc >= 4)
begin Data[7] <= 1'b1; state <= 3'd3;acc <= 8'b0; end
else
begin Data[7] <= 0; state <= 3'd3;acc <= 8'b0; end
end
else
state <= 3'd1;
end
3: begin
if(bit_cnt < 8) begin
Data <= Data >> 1;
state <= 3'd1;
end
else
state <= 0;
end
default:;
endcase
end
always @(posedge Clk or negedge Rst_n) begin
if(Rst_n == 0)
receiv_flag <= 0;
else if(receiv_begin == 1)
receiv_flag <= 1'b1;
else if(bit_cnt == 9 & baud_cnt == BAUD_CNT/9*8)
receiv_flag <= 1'b0;
end
always @(posedge Clk or negedge Rst_n) begin
if(Rst_n == 0)
baud_cnt <= 0;
else if(receiv_flag == 1) begin
if(baud_cnt == BAUD_CNT - 1)
baud_cnt <= 0;
else
baud_cnt <= baud_cnt + 1'b1;
end
else
baud_cnt <= 0;
end
always @(posedge Clk or negedge Rst_n) begin
if(Rst_n == 0) begin
sampel_cnt <= 0;
sampel_en <= 0;
end
else if(receiv_flag == 1) begin
case(baud_cnt)
BAUD_CNT/9*1-1 : begin sampel_cnt <= 0; sampel_en <=1; end
BAUD_CNT/9*2-1 : begin sampel_cnt <= 1; sampel_en <=1; end
BAUD_CNT/9*3-1 : begin sampel_cnt <= 2; sampel_en <=1; end
BAUD_CNT/9*4-1 : begin sampel_cnt <= 3; sampel_en <=1; end
BAUD_CNT/9*5-1 : begin sampel_cnt <= 4; sampel_en <=1; end
BAUD_CNT/9*6-1 : begin sampel_cnt <= 5; sampel_en <=1; end
BAUD_CNT/9*7-1 : begin sampel_cnt <= 6; sampel_en <=1; end
BAUD_CNT/9*8-1 : begin sampel_cnt <= 7; sampel_en <=1; end
BAUD_CNT/9*9-1 : sampel_cnt <= 0;
default:sampel_en <=0;
endcase
end
end
always @(posedge Clk or negedge Rst_n) begin
if(Rst_n == 0)
bit_cnt <= 0;
else if(bit_cnt == 9 & baud_cnt == BAUD_CNT/9*8)
bit_cnt <= 0;
else if(baud_cnt == BAUD_CNT - 1)
bit_cnt <= bit_cnt + 1'b1;
end
always @(posedge Clk or negedge Rst_n) begin
if(Rst_n == 0)
Rx_done <= 0;
else if(bit_cnt == 9 & baud_cnt == BAUD_CNT/9*8)
Rx_done <= 1'b1;
else
Rx_done <= 0;
end
endmodule
LED_6.v
`timescale 1ns / 1ps
module LED_6(
input SCLK,
input RST_N,
input [ 7:0] CTRL_IN,
input [15:0] Time,
output reg [ 7:0] LED
);
parameter DELAY_10US = 500;
parameter COUNT_10MS = 1000;
reg [8:0] count_10us;
reg [15:0] count_time;
reg led_flag;
always @(posedge SCLK or negedge RST_N) begin
if(RST_N == 0)
co