1 //wire [32:0] matrix_row1 = {matrix_p11, matrix_p12,matrix_p13};//just for test
2 //wire [32:0] matrix_row2 = {matrix_p21, matrix_p22,matrix_p23};
3 //wire [32:0] matrix_row3 = {matrix_p31, matrix_p32,matrix_p33};
4 always @(posedge clk or negedge rst_n)
5 begin
6 if(!rst_n)begin
7 {matrix_p11, matrix_p12, matrix_p13} <= 33'h0;
8 {matrix_p21, matrix_p22, matrix_p23} <= 33'h0;
9 {matrix_p31, matrix_p32, matrix_p33} <= 33'h0;
10 end
11 else if(read_frame_href)begin
12 if(read_frame_clken)begin//shift_RAM data read clock enbale
13 {matrix_p11, matrix_p12, matrix_p13} <= {matrix_p12, matrix_p13, row1_data};//1th shift input
14 {matrix_p21, matrix_p22, matrix_p23} <= {matrix_p22, matrix_p23, row2_data};//2th shift input
15 {matrix_p31, matrix_p32, matrix_p33} <= {matrix_p32, matrix_p33, row3_data};//3th shift input
16 end
17 else begin
18 {matrix_p11, matrix_p12, matrix_p13} <= {matrix_p11, matrix_p12, matrix_p13};
19 {matrix_p21, matrix_p22, matrix_p23} <= {matrix_p21, matrix_p22, matrix_p23};
20 {matrix_p31, matrix_p32, matrix_p33} <= {matrix_p31, matrix_p32, matrix_p33};
21 end
22 end
23 else begin
24 {matrix_p11, matrix_p12, matrix_p13} <= 33'h0;
25 {matrix_p21, matrix_p22, matrix_p23} <= 33'h0;
26 {matrix_p31, matrix_p32, matrix_p33} <= 33'h0;
27 end
28 end