fer EP6-OUT buffer to EP2-IN buffer when there is a packet in one of the EP6-OUT buffers, AND
// there is an available EP2-IN buffer. The FIFO status flags update after full packets are transferred.
// Therefore EP2-OUT "Not Empty" means a packet is available, and "EP6-IN "Not Full" means there is an
// available buffer. Using the flags this way handles any packet size and takes multiple buffering
// into account.
if(!(EP2468STAT & bmEP2EMPTY)) // Is EP2-OUT buffer not empty (has at least one packet)?
{
if(!(EP2468STAT & bmEP6FULL)) // YES: Is EP6-IN buffer not full (room for at least 1 pkt)?
{
APTR1H = MSB( &EP2FIFOBUF );
APTR1L = LSB( &EP2FIFOBUF );
AUTOPTRH2 = MSB( &EP6FIFOBUF );
AUTOPTRL2 = LSB( &EP6FIFOBUF );
count = (EP2BCH << 8) + EP2BCL;
// loop EP2OUT buffer data to EP6IN
for( i = 0; i < count; i++ )
{
EXTAUTODAT2 = EXTAUTODAT1; // Autopointers make block transfers easy...
}
EP6BCH = EP2BCH; // Send the same number of bytes as received
SYNCDELAY;
EP6BCL = EP2BCL; // arm EP6IN
SYNCDELAY;
EP2BCL = 0x80; // arm EP2OUT
}
}
}
上面程序是bulkloop中的TD_POLL（）中的程序，此代码执行的就是EP6从EP2中取出数据，再发送到PC机，之前也有提及到，在TD_POLL（）中的程序是供用户控制外部设备使用，那么将TD_POLL（）中的所有代码去除掉，就不会执行从EP2数据发送到EP6数据中了。
上述还有一个地方需要注意，若是定义某个端点为输出，那么在初始化时需要进行2次初始化，如下：
如果是4缓冲，那么这里就要初始化四次。
对于 摄像头 ----》 FPGA -----》USB架构，那么将USB定义为slave FIFO模式，相关初始化参数如下：
void TD_Init(void) // Called once at startup
{
// set the CPU clock to 48MHz, Default 12MHz(Page 333)
//CPUCS = 0x02; //12MHZ CLKOUT ENALBE
//CPUCS = 0x0a; //24MHZ CLKOUT ENALBE
CPUCS = 0x12; //48MHZ CLKOUT ENALBE，时钟不反向，CLKOUT PIN驱动，有时钟输出；
SYNCDELAY;
//Interface Configure(Page 334)
IFCONFIG =0x03; //选择为外部时钟，且时钟频率为30MHz，且为同步slaveFIFO模式,输入IFCLK(5~48MHz)(0000_0011)
//IFCONFIG =0x0B;//选择为外部时钟，且为异步slaveFIFO模式,不需要IFCLK
SYNCDELAY;
//Configure REVCTL for Chip Revision Control(Page 344)
REVCTL = 0x03; //Cypress highly recommends setting both bits to 1
SYNCDELAY;
Rwuen = TRUE; // Enable remote-wakeup
//--------------------------------------------------------
//Se