|
nt_hs+1 ;
87 end
88 end
89
90 assign add_cnt_hs = 1;
91 assign end_cnt_hs = add_cnt_hs && cnt_hs == (COL_NUM)-1 ;
92
93 always @(posedge clk or negedge rst_n) begin
94 if (rst_n==0) begin
95 cnt_vs <= 0;
96 end
97 else if(add_cnt_vs) begin
98 if(end_cnt_vs)
99 cnt_vs <= 0;
100 else
101 cnt_vs <= cnt_vs+1 ;
102 end
103 end
104 assign add_cnt_vs = (end_cnt_hs);
105 assign end_cnt_vs = add_cnt_vs && cnt_vs == (ROW_NUM)-1 ;
106
107
108 /*********************************BRAM相关信号******************************************/
109 //BRAM读取地址计数器
110 always @(posedge clk or negedge rst_n) begin
111 if (rst_n==0) begin
112 cnt_addr <= 0;
113 end
114 else if(add_cnt_addr) begin
115 if(end_cnt_addr)
116 cnt_addr <= 0;
117 else
118 cnt_addr <= cnt_addr+1 ;
119 end
120 end
121
122 assign add_cnt_addr = (ena);
123 assign end_cnt_addr = add_cnt_addr && cnt_addr == 320*240 -1 ;
124
125 assign addra = cnt_addr;
126 assign ena = picture_area;
127
128 //BRAM数据有效指示
129 always @(posedge clk or negedge rst_n)begin
130 if(rst_n==1'b0)begin
131 ram_vld <= 0;
132 end
133 else begin
134 ram_vld <= ena;
135 end
136 end
137 /*********************************VGA输出信号******************************************/
138 //行场同步信号
139 always @(posedge clk or negedge rst_n)begin
140 if(rst_n==1'b0)begin
141 vga_hs <= 1;
142 end
143 else if(add_cnt_hs && cnt_hs == H_A-1)begin
144 vga_hs <= 1;
145 end
146 else if(end_cnt_hs)
147 vga_hs <= 0;
148 end
149
150 always @(posedge clk or negedge rst_n)begin
151 if(rst_n==1'b0)begin
152 vga_vs <= 1;
153 end
154 else if(add_cnt_vs && cnt_vs == V_A-1)begin
155 vga_vs <= 1;
156 end
157 else if(end_cnt_vs)
158 vga_vs <= 0;
159 end
160
161 //R G B寄存器信号
162 always @(posedge clk or negedge rst_n)begin
163 if(rst_n==1'b0)begin
164 r_reg <= 0;
165 g_reg <= 0;
166 b_reg <= 0;
167 end
168 else if(valid_area && !picture_area)begin
169 if(left_half)begin //彩条测试 左半屏幕显示白色
170 r_reg <= 8'b1111_1111;
171 g_reg <= 8'b1111_1111;
172 b_reg <= 8'b1111_1111;
173 end
174 else begin //右半屏幕显示红色
175 r_reg <= 8'b1111_1111;
176 g_reg <= 0;
177 b_reg <= 0;
178 end
179 end
180 else begin//无效区域显示黑色
181 r_reg <= 0;
182 g_reg <= 0;
183 b_reg <= 0;
184 end
185 end
186
187 assign valid_area = cnt_hs >= X0 && cnt_hs < X1 && cnt_vs >= Y0 && cnt_vs < Y1;
188 assign left_half = cnt_hs >= X0 && cnt_hs < X_CENTER;
189 assign picture_area = cnt_hs >= PIC_H_LB && cnt_hs < PIC_H_RB
190 && cnt_vs >= PIC_V_UB && cnt_vs < PIC_V_DB;
191
192 assign vga_r = ram_vld ? {douta[15:11],3'b0} : r_reg;//5bit
193 assign vga_g = ram_vld ? {douta[10:5],2'b0} : g_reg;//6bit
194 assign vga_b = ram_vld ? {douta[4:0],3'b0} : b_reg;//5bit
195
196 //输出控制信号
197 assign vga_clk = ~clk;
198
199 always @(posedge clk or negedge rst_n)begin
200 if(rst_n==1'b0)begin
201 vga_en <= 0;
202 end
203 else if(valid_area)begin
204 vga_en <= 1;
205 end
206 else
207 vga_en <= 0;
208 end
209
210 /*********************************子模块例化 BRAM******************************************/
211
212 blk_mem_gen_0 bram (
213 .clka(clk), // input wire |