1 `timescale 1ns / 1ps
 2 
 3 module cordic_ex_tb();
 4 
 5 parameter CYC = 20;
 6 
 7 reg clk;
 8 reg [16-1:0] din;
 9 reg din_vld;
10 
11 wire signed [17-1:0] dout;
12 wire dout_vld;
13 
14 cordic_ex#(.DIN_W(16),
15            .DOUT_W(16))
16  uut(
17    .clk       (clk)  ,
18    .din       (din)  ,//2Q13
19    .din_vld   (din_vld)  ,
20    .dout      (dout)  ,//2Q14
21    .dout_vld  (dout_vld)     
22 );
23 
24     initial begin
25         clk = 1;
26         forever #(CYC/2) clk = ~clk;
27     end
28 
29     initial begin
30         #1;
31         din = 0;
32         din_vld = 0;
33         #(CYC*10);
34 
35         din_vld = 1;
36         din = 16'b0001010000011011;//pi * 1/5
37         #(CYC*1);
38         din = 16'b1110011011011110;//-pi * 1/4
39         #5;
40         $stop;
41     end
42 
43 endmodule