1 `timescale 1ns / 1ps
2
3 module vga_test_top(
4 input sys_clk_p,
5 input sys_clk_n,
6 input rst_n,
7
8 output vga_hs,
9 output vga_vs,
10 output vga_clk,
11 output vga_en,
12 output [8-1:0] vga_r,
13 output [8-1:0] vga_g,
14 output [8-1:0] vga_b
15 );
16
17 wire clk;
18 wire sys_clk_ibufg;
19 wire locked;
20
21 IBUFGDS #
22 (
23 .DIFF_TERM ("FALSE"),
24 .IBUF_LOW_PWR ("FALSE")
25 )
26 u_ibufg_sys_clk
27 (
28 .I (sys_clk_p),
29 .IB (sys_clk_n),
30 .O (sys_clk_ibufg)
31 );
32
33 clk_wiz_0 pll
34 (
35 // Clock out ports
36 .clk_out1(clk), // output clk_out1
37 // Status and control signals
38 .resetn(rst_n), // input resetn
39 .locked(locked), // output locked
40 // Clock in ports
41 .clk_in1(sys_clk_ibufg)); // input clk_in1
42
43
44 vga_interface#(.DATA_W(8))
45 vga_interface
46 (
47 .clk (clk) ,//65MHz
48 .rst_n (rst_n) ,
49 .vga_clk (vga_clk) ,
50 .vga_en (vga_en) ,
51 .vga_r (vga_r) ,
52 .vga_g (vga_g) ,
53 .vga_b (vga_b) ,
54 .vga_hs (vga_hs) ,
55 .vga_vs (vga_vs)
56 );
57
58
59 endmodule
