ddr1 <= addr1;
w_addr2 <= addr2;
k <= addr2;
state = BUILD_WRITE;
end
else begin
state = BUILD_READ;
i = i - 1;
end
end
else begin
if(data1 <= data2)begin
w_data1 <= data2;
w_data2 <= data1;
w_addr1 <= addr1;
w_addr2 <= addr2;
state = BUILD_WRITE;
end
else begin
state = BUILD_READ;
i = i - 1;
end
end
re <= 0;
end
end
BUILD_WRITE:begin
we = 1;
state <= UPKEEP_READ;
i = i - 1;
end
UPKEEP_READ:begin
//leaf node
if(k > ADDR_WIDTH / 2 ) state <= BUILD_READ;
else begin
state <= UPKEEP_COMPARED;
re = 1;
end
//disable write
we = 0;
addr1 <= k;
addr2 <= 2 * k;
if(k * 2 + 1 <= ADDR_WIDTH) addr3 <= k * 2 + 1;
else addr3 <= 1;
end
UPKEEP_COMPARED:begin
if(r_ok) begin
if(k * 2 + 1 <= ADDR_WIDTH) begin
if(data1 <= data3 && data2 <= data3) begin
w_data1 <= data3;
w_data2 <= data1;
w_addr1 <= addr1;
w_addr2 <= addr3;
k <= addr3;
state <= UPKEEP_WRITE;
end
else if(data1 <= data2 && data3 < data2) begin
w_data1 <= data2;
w_data2 <= data1;
w_addr1 <= addr1;
w_addr2 <= addr2;
k <= addr2;
state <= UPKEEP_WRITE;
end
else state <= BUILD_READ;
end
else begin
if(data1 <= data2)begin
w_data1 <= data2;
w_data2 <= data1;
w_addr1 <= addr1;
w_addr2 <= addr2;
k <= ADDR_WIDTH;
state <= UPKEEP_WRITE;
end
else state <= BUILD_READ;
end
re <= 0;
end
end
UPKEEP_WRITE:begin
we = 1;
state <= UPKEEP_READ;
end
SORT_READY:begin
we = 0;
//condition of ending sort
if(j) state <= SORT_CHANGE;
else state <= COMPLETED;
re <= 1;
addr1 <= 1;
addr2 <= j;
k <= 1;
end
SORT_CHANGE:begin
if(r_ok)begin
w_data1 <= data2;
w_data2 <= data1;
w_addr1 <= addr1;
w_addr2 <= addr2;
state <= SORT_CWRITE;
re <= 0;
end
end
SORT_CWRITE: begin
we = 1;
state <= SORT_READ;
j = j - 1;
end
SORT_READ:begin
//disable write
we = 0;
if(k <= j / 2) begin
state <= SORT_COMPARED;
addr1 <= k;
addr2 <= 2 * k;
if(2 * k + 1 <= j) addr3 <= 2 * k + 1;
re <= 1;
end
else begin
state <= SORT_READY;
end
end
SORT_COMPARED:begin
// big-node
if(r_ok) begin
if(k * 2 + 1 <= j) begin
if(data1 <= data3 && data2 <= data3) begin
w_data1 <= data3;
w_data2 <= data1;
w_addr1 <= addr1;
w_addr2 <= addr3;
state <= SORT_WRITE;
lf <= 1;
end
else if(data1 <= data2 && data3 < data2) begin
w_data1 <= data2;
w_data2 <= data1;
w_addr1 <= addr1;
w_addr2 <= addr2;
state <= SORT_WRITE;
lf <= 0;
end
else state <= SORT_READY;
end
else begin
if(data1 <= data2)begin
w_data1 <= data2;
w_data2 <= data1;
w_addr1 <= addr1;
w_addr2 <= addr2;
state = SORT_WRITE;
lf <= 0;
end
else state <= SORT_READY;
end
re <= 0;
end
end
SORT_WRITE:begin
we = 1;
state <= SORT_READ;
if(lf) k = k * 2 + 1;
else k = k * 2;
end
COMPLETED:begin
state <= COMPLETED;
end
default:begin
state <= ERROR;
end
endcase
end
end
endmodule
寄存器数组部分代码
module ram
#(
parameter ADDR_WIDTH = 12,
parameter DATA_WIDTH = 8
)
(
input [ADDR_WIDTH-1:0] addr1,addr2,addr3,
input [ADDR_WIDTH-1:0] w_addr1,w_addr2,
input we,clk,re,
input [DATA_WIDTH-1:0] w_data1,w_data2,
output reg [DATA_WIDTH-1:0] r_data1,r_data2,r_data3,
output reg w_ok,r_ok
);
reg [DATA_WIDTH-1:0] data[ADDR_WIDTH:1];
initial begin
$readmemh("data.mem",data);