//需要创建对应的文件，用于填充数据
end
always @(posedge clk) begin
if (we ) begin
data[w_addr1] <= w_data1;
data[w_addr2] <= w_data2;
w_ok <= 1;
end
else w_ok <= 0;
if(re) begin
r_data1 <= data[addr1];
r_data2 <= data[addr2];
r_data3 <= data[addr3];
r_ok <= 1;
end
else r_ok <= 0;
end
endmodule
激励模块
module top_tb
#(
parameter ADDR_WIDTH = 12,
parameter DATA_WIDTH = 8
)();
reg clk,rst;
wire [ADDR_WIDTH:1] addr1,addr2,addr3; //read addr
wire [DATA_WIDTH-1:0] data1,data2,data3; //data
wire we; //enable write
wire [DATA_WIDTH-1:0] w_data1,w_data2; //write data
initial begin
clk <= 0;
rst <= 1;
#10;
clk <= 1;
#10;
rst <= 0;
forever begin
clk <= ~clk;
#50;
end
end
top tp(clk,rst,addr1,addr2,addr3,data1,data2,data3,we,w_data1,w_data2);
endmodule
缺陷
实现过程中，最大的缺陷是排序的数不能太多，以为I/O端口有限