这里为了让信号提前一个周期输出，需要使用next_state进行判断.
`timescale 1ns/1ns
module triffic_light
(
input rst_n, //异位复位信号，低电平有效
input clk, //时钟信号
input pass_request,
output wire[7:0]clock,
output reg red,
output reg yellow,
output reg green
);
reg [7:0]cnt;
reg [1:0]state,next_state;
localparam S0=0,S1=1,S2=2,S3=3;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
state <= S0;
else
state <= next_state;
end
always@(*)
begin
case(state)
S0:next_state = (cnt==8)?S3:S0;//reset delay
S1:next_state = (cnt==1)?S3:S1;//green
S2:next_state = (cnt==1)?S1:S2;//yellow
S3:next_state = (cnt==1)?S2:S3;//red
endcase
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
cnt <= 'd10;
else begin
case(state)
S0:cnt <= (cnt == 8)?10:cnt-1;
S1:begin
if(pass_request)
cnt <= 10;
else
cnt <= (cnt == 1)?10:cnt-1;
end
S2:cnt <= (cnt == 1)?60:cnt-1;
S3:cnt <= (cnt == 1)?5:cnt-1;
endcase
end
end
always @(posedge clk or negedge rst_n)
if(~rst_n)begin
red <= 1'd0;
yellow <= 1'd0;
green <= 1'd0;
end else begin
case(next_state)
S0:begin
red <= 1'd0;
yellow <= 1'd0;
green <= 1'd0;
end
S1:begin
red <= 1'd0;
yellow <= 1'd0;
green <= 1'd1;
end
S2:begin
red <= 1'd0;
yellow <= 1'd1;
green <= 1'd0;
end
S3:begin
red <= 1'd1;
yellow <= 1'd0;
green <= 1'd0;
end
default:begin
red <= 1'd0;
yellow <= 1'd0;
green <= 1'd0;
end
endcase
end
assign clock = cnt;
endmodule
`timescale 1ns/1ns
module game_count
(
input rst_n, //异位复位信号，低电平有效
input clk, //时钟信号
input [9:0]money,
input set,
input boost,
output reg[9:0]remain,
output reg yellow,
output reg red
);
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
remain <= 'd0;
else begin
if(set)
remain <= remain + money;
else if(boost)
remain <= (remain<2)?remain:remain-2;
else
remain <= (remain<1)?remain:remain-1;
end
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)begin
yellow <= 1'b0;
red <= 1'b0;
end else begin
if(remain < 10&&remain>10)
yellow <= 1'b1;
else
yellow <= 1'b0;
if((remain<2&&boost)||(remain<1&&~boost))
red <= 1'b1;
else
red <= 1'b0;
end
end
endmodule