module top_module (
input clk,
input reset,
input [31:0] in,
output reg[31:0] out
);
reg [31:0] in_r;
always@(posedge clk)
begin
in_r <= in;
if(reset)
out <= 'd0;
else if(~in&in_r)
out <= (~in&in_r)|out;
end
endmodule
这题确实没想到好的方法,我的写法可能会产生毛刺,因为在边沿的时候q_p和q_n需要时间跳变,这个时候输出就可能有问题,当然,这样仿真还是能通过的,但实际电路中不能这样写。
module top_module (
input clk,
input d,
output q
);
reg q_p,q_n;
always@(posedge clk)
q_p <= d;
always@(negedge clk)
q_n <= d;
assign q = clk?q_p:q_n;
endmodule
module top_module(
input clk,
input d,
output q);
reg p, n;
// A positive-edge triggered flip-flop
always @(posedge clk)
p <= d ^ n;
// A negative-edge triggered flip-flop
always @(negedge clk)
n <= d ^ p;
// Why does this work?
// After posedge clk, p changes to d^n. Thus q = (p^n) = (d^n^n) = d.
// After negedge clk, n changes to d^p. Thus q = (p^n) = (p^d^p) = d.
// At each (positive or negative) clock edge, p and n FFs alternately
// load a value that will cancel out the other and cause the new value of d to remain.
assign q = p ^ n;
// Can't synthesize this.
/*always @(posedge clk, negedge clk) begin
q <= d;
end*/
endmodule