1 `timescale 1ns / 1ps
2
3 module tx_buffer_tb( );
4
5 parameter USER_CLK_CYC = 10,
6 ETH_CLK_CYC = 8,
7 RST_TIM = 3;
8
9 parameter SIM_TIM = 10_000;
10
11 reg user_clk;
12 reg rst_n;
13 reg [32-1:0] din;
14 reg din_vld,din_sop,din_eop;
15 reg [2-1:0] din_mod;
16 wire rdy;
17 reg eth_tx_clk;
18 wire [8-1:0] dout;
19 wire dout_sop,dout_eop,dout_vld;
20 reg [8-1:0] dout_buf [0:1024-1];
21 reg [16-1:0] len [0:100-1];
22 reg [2-1:0] mod [0:100-1];
23 reg err_flag = 0;
24
25 tx_buffer#(.DATA_W(32))//位宽不能改动
26 dut
27 (
28
29 //全局信号
30 .rst_n (rst_n) ,//保证拉低三个时钟周期,否则FIF可能不会正确复位
31 .user_clk (user_clk) ,
32 .din (din) ,
33 .din_vld (din_vld) ,
34 .din_sop (din_sop) ,
35 .din_eop (din_eop) ,
36 .din_mod (din_mod) ,
37 .rdy (rdy) ,
38 .eth_tx_clk (eth_tx_clk) ,
39 .dout (dout) ,
40 .dout_sop (dout_sop) ,
41 .dout_eop (dout_eop) ,
42 .dout_vld (dout_vld)
43 );
44
45 /***********************************时钟******************************************/
46 initial begin
47 user_clk = 1;
48 forever #(USER_CLK_CYC/2) user_clk = ~user_clk;
49 end
50
51 initial begin
52 eth_tx_clk = 1;
53 forever #(ETH_CLK_CYC/2) eth_tx_clk = ~eth_tx_clk;
54 end
55 /***********************************复位逻辑******************************************/
56 initial begin
57 rst_n = 1;
58 #1;
59 rst_n = 0;
60 #(RST_TIM*USER_CLK_CYC);
61 rst_n = 1;
62 end
63
64 /***********************************输入激励******************************************/
65 integer gen_time = 0;
66 initial begin
67 #1;
68 packet_initial;
69 #(RST_TIM*USER_CLK_CYC);
70 packet_gen(20,2);
71 #(USER_CLK_CYC*10);
72 packet_gen(30,1);
73 end
74
75 /***********************************输出缓存与检测******************************************/
76 integer j = 0;
77 integer chk_time = 0;
78 initial begin
79 forever begi