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en
.rd_en(cam_fifo_data_rd_en), // input wire rd_en
.dout(cam_fifo_data_out), // output wire [15 : 0] dout
.full(), // output wire full
.empty(), // output wire empty
.rd_data_count(rd_data_count), // output wire [9 : 0] rd_data_count
.wr_rst_busy(), // output wire wr_rst_busy
.rd_rst_busy() // output wire rd_rst_busy
);
fifo_generator_0 fifo_generator_0_inst (
.clk(m_clk), // input wire clk
.srst(~rst_n), // input wire srst
.din(cam_fifo_data_out), // input wire [15 : 0] din
.wr_en(cam_fifo_data_rd_en_r), // input wire wr_en
.rd_en(~fifo_flag & m_axis_act & m_axis_tready), // input wire rd_en
.dout(fifo_data0), // output wire [15 : 0] dout //m_axis_tdata
.full(), // output wire full
.empty(), // output wire empty
.data_count(fifo_data_count0) // output wire [9 : 0] data_count
);
sobel_filter
#( .DATA_WIDTH(8))
sobel_filter_inst
(
.clk(m_clk),
.reset_p(~rst_n),
.data_in(gray_8b_o),
.data_in_valid(gray_valid),
.data_in_hs(1'b1),
.data_in_vs(1'b1),
.threshold(8'd127),
//--------------------------
.data_out(filter_data_out),
.data_out_valid(filter_data_valid),
.data_out_hs(),
.data_out_vs()
);
fifo_generator_0 fifo_generator_1_inst (
.clk(m_clk), // input wire clk
.srst(~rst_n), // input wire srst
.din({{5{filter_data_out[0]}},{6{filter_data_out[0]}},{5{filter_data_out[0]}}}),// input wire [15 : 0] din
.wr_en(filter_data_valid), // input wire wr_en
.rd_en(fifo_flag & m_axis_act & m_axis_tready), // input wire rd_en
.dout(fifo_data1), // output wire [15 : 0] dout
.full(), // output wire full
.empty(), // output wire empty
.data_count(fifo_data_count1) // output wire [9 : 0] data_count
);
endmodule
sobel_filter.v
`timescale 1ns / 1ps
module sobel_filter
#( parameter DATA_WIDTH = 8)
(
input clk,
input reset_p,
input [DATA_WIDTH - 1:0] data_in,
input data_in_valid,
input data_in_hs,
input data_in_vs,
input [DATA_WIDTH - 1:0] threshold,
//--------------------------
output reg [DATA_WIDTH - 1:0] data_out,
output data_out_valid,
output data_out_hs,
output data_out_vs
);
reg [DATA_WIDTH - 1:0] row0_col0;
reg [DATA_WIDTH - 1:0] row0_col1;
reg [DATA_WIDTH - 1:0] row0_col2;
reg [DATA_WIDTH - 1:0] row1_col0;
reg [DATA_WIDTH - 1:0] row1_col1;
reg [DATA_WIDTH - 1:0] row1_col2;
reg [DATA_WIDTH - 1:0] row2_col0;
reg [DATA_WIDTH - 1:0] row2_col1;
reg [DATA_WIDTH - 1:0] row2_col2;
wire [DATA_WIDTH - 1:0] line0_data;
wire [DATA_WIDTH - 1:0] line1_data;
wire [DATA_WIDTH - 1:0] line2_data;
reg data_in_valid_dly1;
reg data_in_valid_dly2;
reg data_in_valid_dly3;
reg data_in_hs_dly1;
reg data_in_hs_dly2;
reg data_in_hs_dly3;
reg data_in_vs_dly1;
reg data_in_vs_dly2;
reg data_in_vs_dly3;
wire Gx_is_positive;
wire Gy_is_positive;
reg [DATA_WIDTH+1:0] Gx_absolute; //high bit expansion 2bit
reg [DATA_WIDTH+1:0] Gy_absolute; //high bit expansion 2bit
always @(posedge clk or posedge reset_p) begin
if(reset_p) begin
row0_col0 <= 'd0;
row0_col1 <= 'd0;
row0_col2 <= 'd0;
row1_col0 <= 'd0;
row1_col1 <= 'd0;
row1_col2 <= 'd0;
row2_col0 <= 'd0;
row2_col1 <= 'd0;
row2_col2 <= 'd0;
end
else if(data_in_hs && data_in_vs)
if(data_in_valid) begin
row0_col2 <= line0_data;
row0_col1 <= row0_col2;
row0_col0 <= row0_col1;
row1_col2 <= line1_data;
row1_col1 <= row1_col2;
row1_col0 <=
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