不大好。
`timescale 1ns/1ns
module even_div
(
input wire rst ,
input wire clk_in,
output wire clk_out2,
output wire clk_out4,
output wire clk_out8
);
//*************code***********//
reg [2:0]count;
always@(posedge clk_in or negedge rst)
begin
if(~rst)
count <= 0;
else
count <= count + 1;
end
assign clk_out2 = count[0];
assign clk_out4 = count[1:0]>0&&count[1:0]<3;
assign clk_out8 = count>0&&count<5;
//*************code***********//
endmodule
VL38 自动贩售机1
写完发现题目出的有点垃圾，输入d直接在上升沿给值，下降沿恢复，只有半个周期，晕。
状态机折磨了半天，看了看题解，用计数器确实方便多了，一遍过。
`timescale 1ns/1ns
module seller1(
input wire clk ,
input wire rst ,
input wire d1 ,
input wire d2 ,
input wire d3 ,
output reg out1,
output reg [1:0]out2
);
//*************code***********//
reg[2:0]count;
always@(posedge clk or negedge rst)
begin
if(~rst)begin
count <= 0;
out1 <= 0;
out2 <= 0;
end else begin
if(d1)
count <= count + 1;
else if(d2)
count <= count + 2;
else if(d3)
count <= count + 4;
if(count>=3)begin
count <= 0;
out1 <= 1;
out2 <= count -3;
end else begin
out1 <= 0;
out2 <= 0;
end
end
end
//*************code***********//
endmodule
VL39 自动贩售机2
和上一题是一样的，加了一个sel的判断。
`timescale 1ns/1ns
module seller2(
input wire clk ,
input wire rst ,
input wire d1 ,
input wire d2 ,
input wire sel ,
output reg out1,
output reg out2,
output reg out3
);
//*************code***********//
reg [2:0]count;
always@(posedge clk or negedge rst)
begin
if(~rst)begin
count <= 0;
out1 <= 0;
out2 <= 0;
out3 <= 0;
end else begin
if(d1)
count <= count + 1;
else if(d2)
count <= count + 2;
if(sel)begin
if(count >= 5)begin
out1 <= 0;
out2 <= 1;
out3 <= count - 5;
count <= 0;
end else begin
out1 <= 0;
out2 <= 0;
out3 <= 0;
end
end
else begin
if(count >= 3)begin
out1 <= 1;
out2 <= 0;
out3 <= count - 3;
count <= 0;
end else begin
out1 <= 0;
out2 <= 0;
out3 <= 0;
end
end
end
end
//*************code***********//
endmodule
VL40 占空比50%的奇数分频
用两个计数器，一个上升沿计数，一个下降沿计数即可。
不过感觉题目还是有点问题，第一个下降沿复位还没结束，计数器应该不会累加才对。
`timescale 1ns/1ns
module odo_div_or
(
input wire rst ,
input wire clk_in,
output wire clk_out7
);
//*************code***********//
reg clk_out1;
reg clk_out2;
reg [2:0]count1;
reg [2:0]count2;
always@(posedge clk_in or negedge rst)
begin
if(~rst)begin
count1 <= 0;
clk_out1 <= 0;
end else begin
count1 <= (count1 < 6)?(count1 + 1):0;
if(count1 == 3 || count1 ==6)
clk_out1 <= ~clk_out1;
end
end
always@(negedge clk_in or negedge rst)
begin
if(~rst)begin
count2 <= 0;
clk_out2 <= 0;
end else begin
count2 <= (count2 < 6)?(count2 + 1):0;
if(count2 == 3 || count2 ==6)
clk_out2 <= ~clk_out2;
end
end
assign clk_out7 = clk_out1 | clk_out2;
//*************code***********//
endmodule
VL41 任意小数分频
题目给了明示，要先3次8分频再7次9分频，连时钟切换点都给出来了。
`timescale 1ns/1ns
module div_M_N(
input wire clk_in,
input wire rst,
output wire clk_out
);
parameter M_N = 8'd87;
parameter c89 = 8'd24; // 8/9时钟切换点
parameter div_e = 5'd8; //偶数周期
parameter div_o = 5'd9; //奇数周期
//*************code***********//
reg [6:0]count;
reg [3:0]count_e;
reg [3:0]count_o;
reg clk_MN;
always@(posedge clk_in or negedge rst)
begin
if(~rst)
count <= 0;
else
count <= (count < M_N -1)?(coun