【牛客】5 时序逻辑 - Verilog

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【牛客】5 时序逻辑(三)

2023-07-23 13:25:07 【大中小】浏览:128次

t + 1):0; end always@(posedge clk_in or negedge rst) begin if(~rst)begin count_e <= 0; count_o <= 0; clk_MN <= 0; end else begin if(count <= c89 - 1)begin count_e <= (count_e < div_e -1)?(count_e + 1):0; if(count_e == 0||count_e == div_e/2) clk_MN <= ~clk_MN; end else begin count_o <= (count_o < div_o -1)?(count_o + 1):0; if(count_o == 0||count_o == (div_o-1)/2) clk_MN <= ~clk_MN; end end end assign clk_out = clk_MN; //*************code***********// endmodule

VL42 无占空比要求的奇数分频

说是无占空比要求，其实tb还是要求的50%，无语。参照VL40即可。

写完发现其实要求占空比40%，乌鱼子。

`timescale 1ns/1ns

module odd_div (    
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out5
);
//*************code***********//
reg [2:0]count;
reg clk_div;
always@(posedge clk_in or negedge rst)
begin
    if(~rst)begin
        count <= 0;
        clk_div <= 0;
    end else begin
        count <= (count < 4)?(count + 1):0;
        if(count == 0 ||count == 2)
            clk_div <= ~clk_div;
    end
end
assign clk_out5 = clk_div;
//*************code***********//
endmodule

VL43 根据状态转移写状态机-三段式

`timescale 1ns/1ns

module fsm1(
    input wire clk  ,
    input wire rst  ,
    input wire data ,
    output reg flag
);
//*************code***********//
reg[1:0]state,next_state;
localparam S0=0,S1=1,S2=2,S3=3;
always@(posedge clk or negedge rst)
begin
    if(~rst)
        state <= S0;
    else
        state <= next_state;
end
always@(*)
begin
    case(state)
    S0:next_state = data?S1:S0;
    S1:next_state = data?S2:S1;
    S2:next_state = data?S3:S2;
    S3:next_state = data?S0:S3;
    default:next_state = S0;
    endcase
end
always@(posedge clk or negedge rst)
begin
    if(~rst)
        flag <= 0;
    else begin
        if(state == S3 && data)
            flag <= 1;
        else
            flag <= 0;
    end
end
//*************code***********//
endmodule

VL44 根据状态转移写状态机-二段式

两段式把输出和状态转移条件写一起，直接通过组合逻辑输出。

`timescale 1ns/1ns

module fsm2(
    input wire clk  ,
    input wire rst  ,
    input wire data ,
    output reg flag
);

//*************code***********//
reg[2:0]state,next_state;
localparam S0=0,S1=1,S2=2,S3=3,S4=4;
always@(posedge clk or negedge rst)
begin
    if(~rst)
        state <= S0;
    else
        state <= next_state;
end
always@(*)
begin
    case(state)
    S0:begin
        next_state = data?S1:S0;
        flag =0;
    end
    S1:begin
        next_state = data?S2:S1;
        flag =0;
    end
    S2:begin
        next_state = data?S3:S2;
        flag =0;
    end
    S3:begin
        next_state = data?S4:S3;
        flag =0;
    end
    S4:begin
        next_state = data?S1:S0;
        flag = 1;
    end
    default:begin
        next_state = S0;
        flag =0;
    end
    endcase
end


//*************code***********//
endmodule

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