e + 1;
up <= 1;
end
end
endcase
end
end
endmodule
VL30 数据串转并电路
注意时序输出延后一个周期，所以为了时序和题目保持一致，输出时应该输出{data_a,data[5:1]};
`timescale 1ns/1ns
module s_to_p(
input clk ,
input rst_n ,
input valid_a ,
input data_a ,
output reg ready_a ,
output reg valid_b ,
output reg [5:0] data_b
);
reg [2:0]count;
reg [5:0]data;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)begin
ready_a <= 0;
valid_b <= 0;
data_b <= 0;
data <= 0;
count <= 0;
end else begin
ready_a <= 1;
if(valid_a&&ready_a)begin
count <= (count<5)?(count +1):0;
data <= {data_a,data[5:1]};
end
if(count == 5)begin
valid_b <= 1;
data_b <= {data_a,data[5:1]};
end else
valid_b <= 0;
end
end
endmodule
VL31 数据累加输出
注意以下输出后把data_out清空。
`timescale 1ns/1ns
module valid_ready(
input clk ,
input rst_n ,
input [7:0] data_in ,
input valid_a ,
input ready_b ,
output ready_a ,
output reg valid_b ,
output reg [9:0] data_out
);
reg [1:0]count;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)begin
count <= 0;
data_out <= 0;
valid_b <= 0;
end else begin
if(valid_a&&ready_a)begin
if(count == 0)begin
count <= count + 1;
valid_b <= 0;
data_out <= data_in;
end else if(count < 3)begin
count <= count + 1;
data_out <= data_out + data_in;
end else begin
valid_b <= 1;
count <= 0;
data_out <= data_out + data_in;
end
end
end
end
assign ready_a = (~valid_b)||ready_b;
endmodule
VL32 非整数倍数据位宽转换24to128
这道题有点难度，一开始想岔了，以为只要输入六个24位数据，舍弃最后16位，看题解发现最后16位要作为下一个128位数据的开头，晕。
128*3/24=16，所以16个周期为一次循环。
`timescale 1ns/1ns
module width_24to128(
input clk ,
input rst_n ,
input valid_in ,
input [23:0] data_in ,
output reg valid_out ,
output reg [127:0] data_out
);
reg [3:0]count;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
count <= 0;
else if(valid_in)
count <= count + 1;
end
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
valid_out <= 0;
else begin
if(count==5||count==10||count==15)
valid_out <= 1;
else
valid_out <= 0;
end
end
reg [127:0]temp;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)begin
data_out <= 0;
temp <= 0;
end else if(valid_in)begin
temp <= {temp[103:0],data_in};
if(count == 5)
data_out <= {temp[119:0],data_in[23:16]};
else if(count == 10)
data_out <= {temp[111:0],data_in[23:8]};
else if(count == 15)
data_out <= {temp[103:0],data_in};
end
end
endmodule